公开(公告)号：CA1111572A

公开(公告)日：1981-10-27

申请号：CA308848

申请日：1978-08-07

Applicant: IBM

Inventor： NING TAK H ,  OSBURN CARLTON M ,  YU HWA N

IPC: H01L29/78 ,  H01L21/26 ,  H01L21/265 ,  H01L21/268 ,  H01L21/3105 ,  H01L21/336

Abstract: GAS CHARGE NEUTRALIZATION FOR INSULATED GATE FIELD-EFFECT TRANSISTORS Positive charges that appear in the gate silicon oxide insulation of a silicon insulated gate field-effect transistor device may be controlled through neutralization by injecting electrons in to the gate oxide from the substrate after the device is complete and metallized by irradiating the back of the substrate with light in the presence of a voltage bias.

公开(公告)号：DE3274301D1

公开(公告)日：1987-01-02

申请号：DE3274301

申请日：1982-05-24

Applicant: IBM

Inventor： ALTMAN CARL ,  BASSOUS ERNEST ,  OSBURN CARLTON M ,  PLESHKO PETER ,  REISMAN ARNOLD ,  SKOLNIK MARVIN B

IPC: G02B26/10 ,  G02B17/00 ,  G02B26/08 ,  H01J9/20 ,  G02F1/01 ,  G09F9/37 ,  H01J29/12

Abstract: A mirror array light valve comprises a plurality of closely adjacent mirror elements (23) each supported by an individual one of a plurality of post members (19p) disposed in a regular array on a transparent substrate (10). The post members (19p) support the mirror elements (23) under corresponding corners thereof so that all the mirror elements are deflectable in the same direction thereby causing light reflected by the mirror elements to be directed to a single quadrant. The post members are preferably hollow straight- sided cylindrical silicon dioxide structures produced by a self-limiting etching process.

公开(公告)号：CA1115855A

公开(公告)日：1982-01-05

申请号：CA325550

申请日：1979-04-11

Applicant: IBM

Inventor： BASSOUS ERNEST ,  NING TAK H ,  OSBURN CARLTON M

IPC: H01L21/033 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/10 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01J17/00

Abstract: A method, including a sequence of process steps, for fabricating insulated gate field effect transistors having very short effective channel lengths. In a first version of the method, the source and drain regions of the device are opened in one process stop and self-alignment of the source and the drain to the gate is achieved in one masking step. The drain region is then masked and the source side of the channel is implanted to adjust the threshold voltage of the high threshold voltage channel region. In a second version of the method, the source region is opened and self-aligned with the gate prior to the opening of drain region. Implantation to adjust the threshold voltage of the high threshold voltage channel region takes place before the drain region is opened, and then the drain region is opened and self-aligned with the gate in a further masking step. In either version, the threshold voltage is adjustable and the channel length is controlled to be a small value. Y0977-057