公开(公告)号：DE2746778A1

公开(公告)日：1978-05-03

申请号：DE2746778

申请日：1977-10-18

Applicant: IBM

Inventor： CORBIN VIVAN RUTH ,  HITCHNER JAMES EDWARD ,  PATNAIK BISWESWAR ,  TING CHUNG-YU

IPC: H05K3/46 ,  H01L21/28 ,  H01L21/306 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H01L21/90 ,  H01L21/60

Abstract: A method for forming self-aligned via holes which are used to interconnect levels of thin films atop substrates. A first level thin film pattern, typically comprising raised metallic stripes, is formed atop the substrate. A first level dielectric material is then deposited in blanket fashion so that the topology of the insulator conforms to the topology of the pattern. Next, a material such as polymer is deposited which tends to form a planar surface, with a greater thickness of polymer accumulating between the protuberances of the insulator than atop said protuberances. A mask is then applied, exposed and developed at selected regions where via holes are to be formed in the dielectric. A small amount of the polymer is etched, preferably in a plasma, to expose the insulator. Then the latter is etched to form the via holes. Accurately located via holes are formed, even if the mask is misaligned.

公开(公告)号：FR2375717A1

公开(公告)日：1978-07-21

申请号：FR7727691

申请日：1977-09-09

Applicant: IBM

Inventor： CORBIN VIVIAN R ,  HITCHNER JAMES E ,  PATNAIK BISWESWAR ,  TING CHUNG-YU

IPC: H05K3/46 ,  H01L21/28 ,  H01L21/306 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H01L21/82

Abstract: A method for forming self-aligned via holes which are used to interconnect levels of thin films atop substrates. A first level thin film pattern, typically comprising raised metallic stripes, is formed atop the substrate. A first level dielectric material is then deposited in blanket fashion so that the topology of the insulator conforms to the topology of the pattern. Next, a material such as polymer is deposited which tends to form a planar surface, with a greater thickness of polymer accumulating between the protuberances of the insulator than atop said protuberances. A mask is then applied, exposed and developed at selected regions where via holes are to be formed in the dielectric. A small amount of the polymer is etched, preferably in a plasma, to expose the insulator. Then the latter is etched to form the via holes. Accurately located via holes are formed, even if the mask is misaligned.

公开(公告)号：IT1165434B

公开(公告)日：1987-04-22

申请号：IT2813179

申请日：1979-12-18

Applicant: IBM

Inventor： DALAL HORMAZDYAR MINOCHER ,  PATNAIK BISWESWAR ,  SARKARY HOMI GUSTADJI

IPC: H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H05K3/46 ,  H01L

公开(公告)号：DE2966841D1

公开(公告)日：1984-04-26

申请号：DE2966841

申请日：1979-12-10

Applicant: IBM

Inventor： DALAL HORMAZDYAR MINOCHER ,  PATNAIK BISWESWAR ,  SARKARY HOMI GUSTADJI

IPC: H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H05K3/46 ,  H01L21/90 ,  H01L23/52 ,  H05K3/00

公开(公告)号：CA1120611A

公开(公告)日：1982-03-23

申请号：CA337633

申请日：1979-10-15

Applicant: IBM

Inventor： DALAL HORMAZDYAR M ,  PATNAIK BISWESWAR ,  SARKARY HOMI G

IPC: H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H05K3/46 ,  H05K1/11

Abstract: A method for forming feedthrough connections, or via studs, between levels of metallization which are typically formed atop semiconductor substrates. A conductive pattern is formed which includes the first level metallurgy, an etch barrier and the feedthrough metallurgy in the desired first level metallurgical configuration. She via stud metallurgy alone is then patterned, preferably by reactive ion etching, using the etch barrier to prevent etching of the first level metallurgy. An insulator is then deposited around the via studs to form a planar layer of studs and insulator, after which a second level of metallization may be deposited.