公开(公告)号：JPH10303059A

公开(公告)日：1998-11-13

申请号：JP10894598

申请日：1998-04-20

Applicant: IBM

Inventor： DALAL HORMAZDYAR M ,  GAUDENZI GENE JOSEPH ,  GORRELL REBECCA Y ,  TAKACS MARK A ,  TRAVIS JR KENNETH J

IPC: H01G4/228 ,  H01L25/00

Abstract: PROBLEM TO BE SOLVED: To provide a superior direct capacitor attachment by loading a mask so that the opening of the mask exposes the upper face of a high melting point solder ball, making low melting point metallic layer adhere on the high melting point solder ball and forming a capacitor having a low melting point metallic cap. SOLUTION: The high melting point solder ball (solder ball) 18 is formed on the semiconductor moist pad 16 of the multilayer insulating capacitor 10. The solder moist pad 16 is connected to the inner electrodes 11 of the capacitor 10 through a shorting bar 12. The mask 20 having the opening 26 is loaded on the capacitor 10 having a solder ball assembly 14 and the solder ball 18. The uppermost part of the solder ball 18 is exposed and tin 23 is adhered by a solder evaporator. When the solder ball 18 having a tin cap 23 is reflowed, an eutectic alloy 43 is formed on the uppermost part of the solder ball 18 and it can be joined to the circuit 47 of a substrate constituted of copper foil on an organic carrier card 40.

公开(公告)号：JP2002016138A

公开(公告)日：2002-01-18

申请号：JP2001117681

申请日：2001-04-17

Applicant: IBM

Inventor： DALAL HORMAZDYAR M ,  BARENDORA AGARUWARA ,  TERENCE KANE ,  PAUL S MCLOUGHLIN ,  NGUYEN DU ,  RICHARD PROCTER ,  RATHORE HAZARA S ,  YUN-YUU WONG

IPC: C25D5/02 ,  C25D7/12 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide an interconnection with an improved electromigration life. SOLUTION: The formation method of a via stud comprises a) a process for preparing a substrate 10 with at least an attached first level metal 22, wherein the first level metal is provided inside a first insulator 25, b) a process for attaching a layer of a second insulator 35, c) a process for etching a second insulator by etchant for forming a relevance level, wherein the relevance level has at least one line opening 33 and at least one via opening 34, each opening has a side wall and a bottom part, and a first level metal and a part of a first insulator at a lower side of a via opening are exposed by etching, d) a process for etching a part of the exposed first insulator, and e) a process for attaching a liner 51.

公开(公告)号：JP2001351977A

公开(公告)日：2001-12-21

申请号：JP2001117713

申请日：2001-04-17

Applicant: IBM

Inventor： DALAL HORMAZDYAR M ,  BARENDORA AGARUWARA ,  TERENCE KANE ,  PAUL S MCLOUGHLIN ,  NGUYEN DU ,  RICHARD PROCTER ,  RATHORE HAZARA S ,  YUN-YUU WONG

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide an interconnection part that has an improved electromigration life. SOLUTION: This formation method of a via stud includes a process that prepares a substrate 10 having first level adhesion metal 20 (a), a process that allows a layer 35 of an insulator to adhere (b), and a process that etches the insulator by a first etchant to form a related level. The related level has a line opening 33 and a via opening 34. Etching by the first etchant exposes the first level metal at the lower side of the via opening and includes a process that etches the exposed first level metal, so that the opening is formed (d) and a process that allows a linear 51 to adhere (e). The liner lines nearly the entire bottom part of the exposed first level metal and nearly the entire sidewall of the opening of the related level other than the nearly the entire sidewall of the first level metal.

公开(公告)号：JPH1145887A

公开(公告)日：1999-02-16

申请号：JP14391498

申请日：1998-05-26

Applicant: IBM

Inventor： RATHORE HAZARA S ,  DALAL HORMAZDYAR M ,  PAUL S MCLAUGHLIN ,  NGUYEN DU B ,  SMITH RICHARD G ,  SWINTON ALEXANDER J ,  WACHNIK RICHARD A

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To form performance interconnection circuit having a high dimension of sub-half micron having enhanced processing yield and reliability by a method wherein a multilayered interconnection of a copper wire separated from each other by a dielectric insulation is formed, and a contact part with an electrical mechanism in a substrate is formed. SOLUTION: A thin layer 7 of an element, capable of forming a compound between copper and a metal which preferably has a thickness of about 100 to 600 angstroms is adhered to an arbitrarily selected layer 6, and thereafter a thin copper seed layer 8 of a thickness of about 600 to 2000 angstroms is typically stacked. A remaining copper layer 9 is electrically plated after the copper seed layer 8 to bury a groove, or the layer 8, or the layer 8 and the layer 9, may be stacked by a CVD method. Next, this substrate wafer is polished by a chemical mechanical method and all extra metals are removed from a region in which a pattern is not drawn to thereby make a flat structure.

公开(公告)号：DE69332917T2

公开(公告)日：2003-12-24

申请号：DE69332917

申请日：1993-02-01

Applicant: IBM

Inventor： JOSHI RAJIV V ,  CUOMO JEROME J ,  DALAL HORMAZDYAR M ,  HSU LOUIS L

IPC: H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  C23C14/04

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metallizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

公开(公告)号：DE69329663T2

公开(公告)日：2001-05-03

申请号：DE69329663

申请日：1993-02-01

Applicant: IBM

Inventor： JOSHI RAJIV V ,  CUOMO JEROME J ,  DALAL HORMAZDYAR M ,  HSU LOUIS L

IPC: H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485 ,  H01L21/60

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metallizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

公开(公告)号：CA1290414C

公开(公告)日：1991-10-08

申请号：CA595452

申请日：1989-03-31

Applicant: IBM

Inventor： ARNOLD ALLEN J ,  BARIETHER MICHAEL E ,  CHIANG SHIN-WU ,  DALAL HORMAZDYAR M ,  MILLER ROBERT A ,  MONTEGARI FRANK A ,  OBERSCHMIDT JAMES M ,  SHEN DAVID T

IPC: H01G4/12 ,  H01G4/30 ,  H01G1/005 ,  H01G1/147

Abstract: Disclosed is a multilayer capacitor consisting of a plurality of laminae with each of the laminae including a conductive plate portion and a non-conductive sheet portion. The conductive plate portion has at least one tab projecting to at least one edge of the conductive plate portion with the maximum number of tabs per conductive plate portion being limited to avoid excessive lateral congestion. The laminae are divided into different groups with the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the location of the tabs. The laminae are interleaved so that: (a) a lamina from one group alternates with a lamina from a different group, (b) the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, (c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae form rows of tabs, and (d) the tabs from adjacent laminae are not in registry with each other. The capacitor finally includes islands of metallurgy joining selected groups of tabs in each row such that each of the islands covers a portion of each row of tabs. FI9-88-005

公开(公告)号：CA1111570A

公开(公告)日：1981-10-27

申请号：CA307591

申请日：1978-07-18

Applicant: IBM

Inventor： DALAL HORMAZDYAR M ,  GHAFGHAICHI MAJID ,  KASPRZAK LUCIAN A ,  WIMPFHEIMER HANS

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/285 ,  H01L21/338 ,  H01L21/60 ,  H01L23/532 ,  H01L29/43 ,  H01L29/45 ,  H01L29/47 ,  H01L29/872 ,  H01L29/18

Abstract: TANTALUM SEMICONDUCTOR CONTACTS AND METHOD FOR FABRICATING SAME A silicon semiconductor device having contacts which include tantalum. The tantalum is useful in particular for fabricating Schottky barrier diodes having a low barrier height. The method includes: precleaning the silicon substrate prior to depositing the tantalum; depositing the tantalum at low pressure and low substrate temperature to avoid oxidation of the tantalum; and sintering the contact to reduce any interfacial charges and films remaining between the silicon and tantalum. When a metal which reacts with silicon during processing, such as aluminum, is used as interconnection metallurgy, a layer of chrome must be deposited between the tantalum and aluminum.

公开(公告)号：DE69333604D1

公开(公告)日：2004-09-30

申请号：DE69333604

申请日：1993-02-01

Applicant: IBM

Inventor： JOSHI RAJIV V ,  CUOMO JEROME J ,  DALAL HORMAZDYAR M ,  HSU LOUIS L

IPC: H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485 ,  H01L21/60

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metallizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

公开(公告)号：DE69332917D1

公开(公告)日：2003-05-28

申请号：DE69332917

申请日：1993-02-01

Applicant: IBM

Inventor： JOSHI RAJIV V ,  CUOMO JEROME J ,  DALAL HORMAZDYAR M ,  HSU LOUIS L

IPC: H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  C23C14/04

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metallizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.