公开(公告)号：WO03021672A3

公开(公告)日：2003-07-24

申请号：PCT/GB0203837

申请日：2002-08-19

Applicant: IBM ,  IBM UK

Inventor： ALCOE DAVID ,  LI LI ,  SATHE SANJEEV BALWANT

IPC: H01L23/00 ,  H01L23/373 ,  H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/3735 ,  H01L2224/16 ,  H01L2924/01025 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0203 ,  H05K1/0271 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/2009

Abstract: An electronic package and method of making same in which a circuitized substrate having a first stiffness includes a plurality of electrically conductive circuit members on a first portion of the circuitized substrate and is adapted for having solder connections thereon and for being electrically connected to a semiconductor chip. A stiffener layer having a second stiffness is positioned on a second portion of the circuitized substrate relative to the first portion, the second stiffness of the stiffener layer distributing a portion of the first stiffness of said circuitized substrate so as to substantially prevent failure of the solder connections between the electrically conductive circuit members and the semiconductor chip during operation of the electronic package.

Abstract translation: 一种电子封装及其制造方法，其中具有第一刚度的电路化衬底包括在电路化衬底的第一部分上的多个导电电路构件，并且适于在其上具有焊接连接并且用于电连接到半导体芯片 。 具有第二刚度的加强层相对于第一部分位于电路化基板的第二部分上，加强层的第二刚度分布所述电路化基板的第一刚度的一部分，以便基本上防止焊料的故障 在电子封装的操作期间导电电路部件与半导体芯片之间的连接。

公开(公告)号：JP2004056127A

公开(公告)日：2004-02-19

申请号：JP2003181896

申请日：2003-06-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： INFANTOLINO WILLIAM ,  LE LE ,  ROSSER STEVEN G ,  SATHE SANJEEV BALWANT

IPC: H01L21/60 ,  H01L21/56 ,  H01L23/10 ,  H01L23/498

CPC classification number: H01L23/49838 ,  H01L21/563 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/0401

Abstract: PROBLEM TO BE SOLVED: To provide an electronic package structure having a module arrangement and its forming method.
SOLUTION: This electronic package structure reduces stress which occurs at a chip 12, an underfill 18, a ball grid array connection, and a flexible substrate 14 made of an organic material. The stress causes potential delamination problems due to thermally induced warpage among components in a module structure. By reducing the stress, no warpage occurs among components in the electronic package, resulting in no delamination problems.
COPYRIGHT: (C)2004,JPO

公开(公告)号：PL323321A1

公开(公告)日：1998-06-22

申请号：PL32332197

申请日：1997-11-25

Applicant: IBM

Inventor： ALCOE DAVID JAMES ,  SATHE SANJEEV BALWANT

IPC: H01L21/56 ,  H01L23/12 ,  H05K7/20 ,  H01L23/34 ,  H01L23/36 ,  H01L23/367 ,  H01L23/373 ,  H01L23/40 ,  H01L23/433

Abstract: An electronic package wherein an electronic device (e.g., chip) on a circuitized substrate of the package is thermally coupled to a heatsink in a separable manner using a plurality of compressible, thermally conductive members (e.g., solder balls). These members are compressed and permanently deformed as part of the thermal coupling.

公开(公告)号：CZ290553B6

公开(公告)日：2002-08-14

申请号：CZ363897

申请日：1997-11-17

Applicant: IBM

Inventor： ALCOE DAVID JAMES ,  SATHE SANJEEV BALWANT

IPC: H05K7/20 ,  H01L21/56 ,  H01L23/12 ,  H01L23/34 ,  H01L23/36 ,  H01L23/367 ,  H01L23/373 ,  H01L23/40 ,  H01L23/433

Abstract: In the present invention there is disclosed an electronic package assembly (10) wherein an electronic device (18) (for example a chip) on a circuitized substrate of the package assembly (10) is thermally coupled to a heatsink (22) in a separable manner using a plurality of compressible, thermally conductive members (26) (for example solder balls). These members (26) are compressed and permanently deformed as part of the thermal coupling. Disclosed is also a process for producing such electronic package assembly, which process comprises manufacture of a substrate with conductors placed thereon, placing an electronic device on such circuitized substrate and connecting thereof to the conductors, thermal coupling of a heatsink to the electronic device in a separable manner, placing compressible, thermally conductive members between the electronic device and the heatsink and exerting compressible force on this package assembly.

公开(公告)号：CZ9703638A3

公开(公告)日：1998-11-11

申请号：CZ363897

申请日：1997-11-17

Applicant: IBM

Inventor： ALCOE DAVID JAMES ,  SATHE SANJEEV BALWANT

IPC: H05K7/20 ,  H01L21/56 ,  H01L23/12 ,  H01L23/34 ,  H01L23/36 ,  H01L23/367 ,  H01L23/373 ,  H01L23/40 ,  H01L23/433

CPC classification number: H01L23/3733 ,  H01L21/563 ,  H01L23/3677 ,  H01L23/4093 ,  H01L23/433 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/01322 ,  Y10T156/1089 ,  Y10T156/1093 ,  H01L2924/00

公开(公告)号：SG66409A1

公开(公告)日：1999-07-20

申请号：SG1997004056

申请日：1997-11-14

Applicant: IBM

Inventor： ALCOE DAVID JAMES ,  SATHE SANJEEV BALWANT

IPC: H01L21/56 ,  H01L23/12 ,  H01L23/34 ,  H05K7/20 ,  H01L23/36 ,  H01L23/367 ,  H01L23/373 ,  H01L23/40 ,  H01L23/433 ,  H01L23/10

Abstract: An electronic package wherein an electronic device (e.g., chip) on a circuitized substrate of the package is thermally coupled to a heatsink in a separable manner using a plurality of compressible, thermally conductive members (e.g., solder balls). These members are compressed and permanently deformed as part of the thermal coupling.

公开(公告)号：HU9701376A2

公开(公告)日：1998-07-28

申请号：HU9701376

申请日：1997-08-11

Applicant: IBM

Inventor： ALCOE DAVID JAMES ,  SATHE SANJEEV BALWANT

IPC: H05K7/20 ,  H01L21/56 ,  H01L23/12 ,  H01L23/34 ,  H01L23/36 ,  H01L23/367 ,  H01L23/373 ,  H01L23/40 ,  H01L23/433 ,  H01L23/02

Abstract: An electronic package wherein an electronic device (e.g., chip) on a circuitized substrate of the package is thermally coupled to a heatsink in a separable manner using a plurality of compressible, thermally conductive members (e.g., solder balls). These members are compressed and permanently deformed as part of the thermal coupling.

公开(公告)号：HU9701376D0

公开(公告)日：1997-10-28

申请号：HU9701376

申请日：1997-08-11

Applicant: IBM

Inventor： ALCOE DAVID JAMES ,  SATHE SANJEEV BALWANT

IPC: H05K7/20 ,  H01L21/56 ,  H01L23/12 ,  H01L23/34 ,  H01L23/36 ,  H01L23/367 ,  H01L23/373 ,  H01L23/40 ,  H01L23/433

Abstract: An electronic package wherein an electronic device (e.g., chip) on a circuitized substrate of the package is thermally coupled to a heatsink in a separable manner using a plurality of compressible, thermally conductive members (e.g., solder balls). These members are compressed and permanently deformed as part of the thermal coupling.

公开(公告)号：MY118259A

公开(公告)日：2004-09-30

申请号：MYPI9705477

申请日：1997-11-14

Applicant: IBM

Inventor： ALCOE DAVID JAMES ,  SATHE SANJEEV BALWANT

IPC: H01L23/10 ,  H01L21/44 ,  H05K7/20 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L23/12 ,  H01L23/34 ,  H01L23/36 ,  H01L23/367 ,  H01L23/373 ,  H01L23/40 ,  H01L23/433

Abstract: AN ELECTRONIC PACKAGE (10,10'',10")WHEREIN AN ELECTRONIC DEVICE (18)(E.G., CHIP) ON A CIRCUITIZED SUBSTRATE (12) OF THE PACKAGE IS THERMALLY COUPLED TO A HEATSINK (22) IN A SEPARABLE MANNER USING A PLURALITY OF COMPRESSIBLE, THERMALLY CONDUCTIVE MEMBERS (26,26'',26")(E.G., SOLDER BALLS). THESE MEMBERS ARE COMPRESSED AND PERMANENTLY DEFORMED AS PART OF THE THERMAL COUPLING.

公开(公告)号：AU2002329376A1

公开(公告)日：2003-03-18

申请号：AU2002329376

申请日：2002-08-19

Applicant: IBM

Inventor： ALCOE DAVID ,  SATHE SANJEEV BALWANT ,  LI LI

IPC: H01L23/00 ,  H01L23/373 ,  H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H01L23/498

Abstract: An electronic package and method of making same in which a circuitized substrate having a first stiffness includes a plurality of electrically conductive circuit members on a first portion of the circuitized substrate and is adapted for having solder connections thereon and for being electrically connected to a semiconductor chip. A stiffener layer having a second stiffness is positioned on a second portion of the circuitized substrate relative to the first portion, the second stiffness of the stiffener layer distributing a portion of the first stiffness of said circuitized substrate so as to substantially prevent failure of the solder connections between the electrically conductive circuit members and the semiconductor chip during operation of the electronic package.