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    COMBINATIONAL CIRCUIT, ENCRYPTION CIRCUIT, ITS GENERATION METHOD AND PROGRAM
    2.
    发明专利
    COMBINATIONAL CIRCUIT, ENCRYPTION CIRCUIT, ITS GENERATION METHOD AND PROGRAM 审中-公开

    公开(公告)号：JP2003223100A

    公开(公告)日：2003-08-08

    申请号：JP2002017959

    申请日：2002-01-28

    Applicant: IBM

    Inventor： MORIOKA SUMIO ,  SATO AKASHI ,  CHO KO

    IPC: G06F17/50 ,  G09C1/00 ,  H03K19/0952 ,  H03K19/20 ,  H04L9/06

    Abstract: PROBLEM TO BE SOLVED: To provide a technique for realizing a high speed combinational circuit including an S-Box and for simultaneously generating an RO-BDD prescribing the circuit structure of the combinational circuit. SOLUTION: The combinational circuit is provided with the number of independent selector groups 100 to 170 corresponding to the number of output bits that individually generates the output bits and a driver chain that supplies primary input to the respective selector groups 100 to 170, the respective selector groups 100 to 170 are provided with a plurality of selectors 101 connected by forming the number of stages equal to or less than the number of bits of the primary input and selected signals of the selectors 101 at the respective stages are driven by one primary input. COPYRIGHT: (C)2003,JPO

    CONTROL CIRCUIT OF ASSOCIATIVE MEMORY AND ASSOCIATIVE MEMORYDEVICE
    3.
    发明专利
    CONTROL CIRCUIT OF ASSOCIATIVE MEMORY AND ASSOCIATIVE MEMORYDEVICE 失效

    公开(公告)号：JPH08147986A

    公开(公告)日：1996-06-07

    申请号：JP29255694

    申请日：1994-11-28

    Applicant: IBM

    Inventor： SATO AKASHI

    IPC: G11C15/00 ,  G11C15/04

    Abstract: PURPOSE: To reduce the dissipation power. CONSTITUTION: A timing control signal SR is set to a low level to turn on a P-MOSFET 62 and to turn ff an N-MOSFET 60, and the potential VMATCH1 of NOT circuit 64 side of a matching line is pulled up to a power source voltage VDD at the N-MOSFET 60 as a boundary. Comparison is conducted by an associative memory cell 28 during this period. The N-MOSFET 42 is turned on or off in response to the comparison result. Then, the signal SR is set to high level to turn off the P-MOSFET 62 and to turn on the N-MOSFET 60. Thus, if the N-MOSFET 42 is turned on, the potentials VMATCH1 and VMATCH are lowered to a ground level, but a through current is prevented by the off of the potential VMATCH. If the N-MOSFET 42 is off, VMATCH1 is pulled up to VDD-Vth (Vth is the threshold value voltage of the N-MOSFET60), V is maintained at VDD by NOT circuit 64 and P-MOSFET 66, and the signal representing the comparison result is output from the NOT circuit 64.

    ARITHMETIC CIRCUIT AND ARITHMETIC METHOD
    4.
    发明专利
    ARITHMETIC CIRCUIT AND ARITHMETIC METHOD 失效

    公开(公告)号：JP2002207589A

    公开(公告)日：2002-07-26

    申请号：JP2000386069

    申请日：2000-12-19

    Applicant: IBM

    Inventor： TAKANO KOJI ,  SATO AKASHI

    IPC: G06F7/527 ,  G06F7/44 ,  G06F7/72 ,  G06F9/30 ,  G06F9/38 ,  G06F12/06 ,  G06F7/52

    Abstract: PROBLEM TO BE SOLVED: To solve the bottleneck of a memory access in a Montgomery arithmetic circuit while using a 2-ports or single-port general memory. SOLUTION: The circuit comprises two memories 7 and 8, and the variables necessary to be read from the memories of variables necessary for operation are recorded in different memories. In the same reading stage of pipeline processing, a variable is read from the memory 7 to a resister 5, and the other variable is read from the memory 8 to the other resister.

    CIRCUIT FOR CALCULATING REMAINDER MODULUS N OF C-TH POWER OF B
    5.
    发明专利
    CIRCUIT FOR CALCULATING REMAINDER MODULUS N OF C-TH POWER OF B 失效

    公开(公告)号：JPH10260818A

    公开(公告)日：1998-09-29

    申请号：JP24511397

    申请日：1997-09-10

    Applicant: IBM

    Inventor： KOBAYASHI YOSHINAO ,  SATO AKASHI ,  NIIJIMA HIDETO

    IPC: G06F7/72 ,  G09C1/00

    Abstract: PROBLEM TO BE SOLVED: To fast calculate a remainder of n of the C-th power of B. SOLUTION: This circuit has a 1st circuit 100, which calculates a remainder to module n of B, holds a result B1, shifts a holding value, calculates a value to be congru to modulus n and repeats processing to hold a result, a 2nd circuit 110 which accumulates calculation results of the 1st circuit when a prescribed bit of a 1st register 120 that makes an initial value B1 is one and a 3rd circuit 150 which accumulates results of the 1st circuit when the output volue of a C output circuit 140 is one and the prescribed bit of a 2nd register 160 whose initial value is one is one. The prescribed bits of the 1st and 2nd registers are shifted in the direction from the LSB of a stored value to MSB, a value to be congruous to modulus n of the accumulated result of the 2nd circuit a method and is congruous is made the holding value of the 1st circuit and stored in the 1st register when the processing of the MSB of a value that is stored by the 1st register is finished, the output of a C output circuit is changed to a value that is shifted in the direction from the LSB of C to MSB, and a value to be congruous to modulus n of the accumulated results of the 3rd circuit is stored in the 2nd register when the output value of the C output circuit is one.

    CARRY SKIP ADDER
    6.
    发明专利
    CARRY SKIP ADDER 失效

    公开(公告)号：JPH11143685A

    公开(公告)日：1999-05-28

    申请号：JP9183798

    申请日：1998-04-03

    Applicant: IBM

    Inventor： KOBAYASHI YOSHINAO ,  SATO AKASHI ,  MUNETO SEIJI

    IPC: G06F7/50 ,  G06F7/508

    Abstract: PROBLEM TO BE SOLVED: To provide a high-speed carry skip adder of two or more stages. SOLUTION: Plural ripple adders are provided, at least a part of the ripple adders among the plural ripple adders are grouped and carry signals are transmitted to a certain group or the group of a one higher order. Then, this adder is provided with a circuit for calculating C=C2+F.C1 by using the carry signals C1 from the certain group to the group of the one higher order, signals F for indicating whether or not the output of a full adder within the group of the one higher order is present as 1 and the carry signals C2 relating to the ripple adder of a highest order within the group of the one higher order.

    DATA RETRIEVAL APPARATUS AS WELL AS APPARATUS AND METHOD FOR DATA COMPRESSION
    7.
    发明专利
    DATA RETRIEVAL APPARATUS AS WELL AS APPARATUS AND METHOD FOR DATA COMPRESSION 失效

    公开(公告)号：JPH07114577A

    公开(公告)日：1995-05-02

    申请号：JP31994493

    申请日：1993-12-20

    Applicant: IBM

    Inventor： SATO AKASHI ,  NIIJIMA HIDETO

    IPC: H03M7/46 ,  G06F17/30 ,  G06T9/00 ,  H03M7/30

    Abstract: PURPOSE: To enable the retrieval of data at a high speed. CONSTITUTION: When retrieving a retrieval character string (ABCA) corresponding to a character string (BABCABB...), which is successively stored in the associated memory cell sequences of an associated memory 26, to be retrieved, the data of the 1st character (A) in the retrieval character string are inputted to a buffer 56 and a comparing operation is performed for all the cell sequences. The operation of comparison with the next character (B) is performed only for the cell sequence of addresses (2) and (5) adjacent with the cell sequence coincident the last time. Similarly, the operation of comparison with the next character (C) is performed only for the cell sequence of addresses (3) and (6). Further, the comparison with the final character (A) is performed only for the cell sequence of an address (4) adjacent to the cell sequence of the address (3) coincident the last time. In this case, even when the length of the retrieval character string is a variable length, only the number of times to repeat the comparing operation is changed and especially when the character string to be retrieved is long, retrieval processing is completed within an extremely short time in comparison with conventional device.

    BATCHED-ERASURE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    8.
    发明专利
    BATCHED-ERASURE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效

    公开(公告)号：JPH06111589A

    公开(公告)日：1994-04-22

    申请号：JP24311892

    申请日：1992-09-11

    Applicant: IBM

    Inventor： NIIJIMA HIDETO ,  TOYOOKA TAKASHI ,  SATO AKASHI ,  SAKAGAMI YOSHIKATSU

    IPC: G11C17/00 ,  G06F11/10 ,  G11C16/02 ,  G11C16/06 ,  G11C16/16 ,  G11C16/22 ,  G11C29/00 ,  G11C29/04 ,  G11C29/42 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: PURPOSE: To obtain the efficient redundant constitution of a batch erasing type nonvolatile semiconductor storage device. CONSTITUTION: The array of a memory cell 31 is physically divided into a data area 36 and a tag area 37 to separately batch-erase the respective areas while sharing a word line 32. In the unit of the areas 36 and 37 sharing one word line, the area 37 holds positional information of a defective memory cell in the area 36. Based on this information, a system executes the using avoiding processing of the defective memory cell. Defective memory cell information is programmed in an inspection process after producing a chip, and ECC is written in the area 37 with respect to this defective memory cell information. By writing fixed data in the area 37, the using prohibition of the area 36 sharing the word line with the area 37 is reported to the system. Even when the area 36 is batch-erased, the area 37 is not erased and defective memory cell positional information is held.

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