公开(公告)号：JP2003018151A

公开(公告)日：2003-01-17

申请号：JP2001191828

申请日：2001-06-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： NIIJIMA HIDETO ,  ETO HIROAKI

IPC: G06F12/14 ,  G06F21/24 ,  G11B20/10 ,  H04L9/32

Abstract: PROBLEM TO BE SOLVED: To enable a system device to certify an external storage device, by inhibiting the external storage device from operating, except the combination with specified system devices.
SOLUTION: This certification method is performed between a secure HDD 20 for performing the write and read of data and a set top box 10 for accessing this secure HDD 20; the set top box 10 transmits random numbers generated to the secure HDD 20, and the secure HDD 20 transmits the information, which is coded with a secret key, after performing processing under a certain rule to the transmitted random numbers to the set top box 10; and the set top box 10 decodes the received information, using a secrete key; and based on the decoded information, it recognizes that the processing has been conducted in conformity with a fixed rule, and the secure HDD 20 and the set top box 10 hold the same secret key with each other.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：除了与指定的系统设备的组合之外，通过禁止外部存储设备的操作，使系统设备能够验证外部存储设备。 解决方案：该认证方法在用于执行数据的写入和读取的安全HDD 20和用于访问该安全HDD 20的机顶盒10之间执行; 机顶盒10将生成的随机数发送到安全HDD 20，并且安全HDD 20在以特定规则执行处理之后，将其发送的随机数发送到机顶盒10 ; 并且机顶盒10使用分密密钥解码所接收的信息; 并且基于解码的信息，它识别出已经按照固定规则进行了处理，并且安全HDD 20和机顶盒10彼此保持相同的秘密密钥。

公开(公告)号：JPH07295763A

公开(公告)日：1995-11-10

申请号：JP10632494

申请日：1994-04-22

Applicant: IBM

Inventor： NIIJIMA HIDETO ,  MATSUO NOBUYUKI ,  SHIMADA MAYUMI

IPC: G06F3/06 ,  G06F11/10

Abstract: PURPOSE: To improve the rewrite speed of a disk array device (RAID). CONSTITUTION: Access to a data disk is made apparently once by dividing a disk to read old data and a disk to write new data and an external semiconductor storage device whose write performance is considerably improved is used for a parity disk to make two accesses within an access time of the data disk once complete. A data array dividing data into N sequentially in the unit of one or a plurality of sectors is stored in each sector of N-sets of magnetic disks and the parity is stored in a parity disk. In the disk array device as above, (N+1) sets of magnetic disk devices for data storage and the data array is stored in sectors of the N-sets of magnetic disk devices and sectors of one magnetic disk device are used for redundant sectors.

公开(公告)号：JPH06250798A

公开(公告)日：1994-09-09

申请号：JP3522893

申请日：1993-02-24

Applicant: IBM

Inventor： NIIJIMA HIDETO ,  ASANO HIDEO ,  SAKAGAMI YOSHIKATSU ,  TOYOOKA TAKASHI

IPC: G06F3/08 ,  G06F3/06 ,  G06F12/00 ,  G06F12/02 ,  G11C16/02 ,  G11C16/10 ,  G11C17/00 ,  G11C16/06

Abstract: PURPOSE: To discriminate an invalid sector from a valid sector without using a method for overwriting by ensuring a cluster information sector in each cluster, applying a sequence number to the cluster so as not to be doubled, and writing the sequence number assigned to the cluster in the cluster information sector of each cluster. CONSTITUTION: A batch delete type nonvolatile memory 20 can be deleted by each cluster unit, a cluster information sector is ensured in each of the N pieces of clusters, a sequence number is preliminarily applied to the N pieces of clusters so as not to be overlapped, and the sequence number of the cluster is written in the cluster information sector of each cluster. At the time of deleting a certain cluster, a controller 30 maintains the sequence number of the cluster at first, and at the time of initializing the deleted cluster, the controller 30 writes a value larger than the present maximum sequence number in the cluster information sector as the sequence number of the cluster. The controller 30 writes user data according to the sequence number of the physical address of the sector.

公开(公告)号：JPH06131266A

公开(公告)日：1994-05-13

申请号：JP25628492

申请日：1992-09-25

Applicant: IBM

Inventor： NIIJIMA HIDETO ,  SATO AKASHI ,  SAKAGAMI YOSHIKATSU

IPC: G06F12/08 ,  G06F9/445 ,  G06F12/00 ,  G06F12/02 ,  G06F12/10 ,  G06F12/12

Abstract: PURPOSE: To execute a program without reading it on a main memory unit and to unitarily manage the program and data on a randomly accessible and rewritable memory without distinguishing them. CONSTITUTION: A computer system is provided with a CPU for converting addresses by referring to a real/virtual address conversion table provided with a page table 25 and an external storage device for using the randomly accessible and rewritable memory connected to the CPU. The page table 25 is constituted so as to make the codes of the program be continuous on the virtual address space of the CPU corresponding to an execution order, and by referring to the real/virtual address conversion table provided with the page table, the program stored in the external storage device is read from the external storage device and executed by using a virtual address. Also, the real address of the CPU is allocated only to the data area of the randomly accessible memory.

公开(公告)号：DE69223287D1

公开(公告)日：1998-01-08

申请号：DE69223287

申请日：1992-07-01

Applicant: IBM

Inventor： SAKAUE YOSHINORI ,  NIIJIMA HIDETO

IPC: G06F3/08 ,  G06F3/06 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/12 ,  G11C16/02 ,  G11C16/10 ,  G11C16/34 ,  G11C17/00

Abstract: To provide an external storage system using a semiconductor memory in which the data reading and writing between the host CPU can be processed faster than the conventional magnetic disk, and only a particular sector is not frequently written and erased so that the whole memory is effectively used over a long period of time, an address control scheme is introduced in which flexibility is given to the address relation between the host CPU and the external storage and the physical address of the semiconductor memory is not one-sidedly determined by the logical address possessed by the command of the host CPU.

公开(公告)号：JPH10260818A

公开(公告)日：1998-09-29

申请号：JP24511397

申请日：1997-09-10

Applicant: IBM

Inventor： KOBAYASHI YOSHINAO ,  SATO AKASHI ,  NIIJIMA HIDETO

IPC: G06F7/72 ,  G09C1/00

Abstract: PROBLEM TO BE SOLVED: To fast calculate a remainder of n of the C-th power of B. SOLUTION: This circuit has a 1st circuit 100, which calculates a remainder to module n of B, holds a result B1, shifts a holding value, calculates a value to be congru to modulus n and repeats processing to hold a result, a 2nd circuit 110 which accumulates calculation results of the 1st circuit when a prescribed bit of a 1st register 120 that makes an initial value B1 is one and a 3rd circuit 150 which accumulates results of the 1st circuit when the output volue of a C output circuit 140 is one and the prescribed bit of a 2nd register 160 whose initial value is one is one. The prescribed bits of the 1st and 2nd registers are shifted in the direction from the LSB of a stored value to MSB, a value to be congruous to modulus n of the accumulated result of the 2nd circuit a method and is congruous is made the holding value of the 1st circuit and stored in the 1st register when the processing of the MSB of a value that is stored by the 1st register is finished, the output of a C output circuit is changed to a value that is shifted in the direction from the LSB of C to MSB, and a value to be congruous to modulus n of the accumulated results of the 3rd circuit is stored in the 2nd register when the output value of the C output circuit is one.

公开(公告)号：JPH09160723A

公开(公告)日：1997-06-20

申请号：JP31779795

申请日：1995-12-06

Applicant: IBM JAPAN

Inventor： MUNETO SEIJI ,  NIIJIMA HIDETO ,  MURATA HIROKI ,  TAKAHASHI NOBUAKI

IPC: G06F12/16 ,  G06F3/06 ,  G06F11/10

Abstract: PROBLEM TO BE SOLVED: To prevent a data storage system from being complicated by transferring fast the data via data buses and also facilitating the control of the timing of the system. SOLUTION: The mutual synchronization of accesses is secured among storage means 13 to 17 which store the data. For this purpose, the data buses 11 and 12 are prepared to transfer the data together with an input/output means 21 which transfers the plural data series to the buses 11 and 12 with interleave, and a latch means 23 which is provided at plural stages and in series between the means 13 to 17 and the buses 11 and 12 and hold the data respectively.

公开(公告)号：JPH08202497A

公开(公告)日：1996-08-09

申请号：JP1043595

申请日：1995-01-26

Applicant: IBM JAPAN

Inventor： MUNETO SEIJI ,  NIIJIMA HIDETO ,  MURATA HIROKI ,  TAKAHASHI NOBUAKI

IPC: G06F12/16 ,  G06F3/06 ,  G06F11/10 ,  G06F13/16

Abstract: PURPOSE: To facilitate transfer operation and restore data efficiently at a high speed in the case of fault occurrence by providing plural storage means, a data bus, and a selecting means having a function for parity arithmetic operation. CONSTITUTION: Two channels of 4-channel crossbar switches 11a and 11b having an exclusive OR operation function are connected to data buses DDO and DD1 as common buses. Other two channels of the crossbar switch 11a as the selecting means are connected to drives HDDO and HDD1. Other two channels of the crossbar switch 11b are connected to drives HDD2 and HDD3. Further, the crossbar switches 11a and 11b are controlled with an address signal and a control signal outputted from a data bus controller 13, and connections in optional combinations of drives and data buses are enabled. Thus, the selecting means itself is provided with the function for parity arithmetic operation.

公开(公告)号：JPH0527924A

公开(公告)日：1993-02-05

申请号：JP19731891

申请日：1991-07-12

Applicant: IBM

Inventor： SAKAGAMI YOSHIKATSU ,  NIIJIMA HIDETO

IPC: G06F3/08 ,  G06F3/06 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/12 ,  G11C16/02 ,  G11C16/10 ,  G11C16/34 ,  G11C17/00

Abstract: PURPOSE: To make it possible to perform reading out and writing of data with a host CPU, to process at a speed higher than the speed of the conventional magnetic disks and to make the entire memory usable effectively over a long period of time without allowing only the specific sector to be frequently written and erased. CONSTITUTION: An address control system which imparts flexibility to the address relation between the host CPU and an external memory device and prevents the physically address of a semiconductor memory is not one-sidedly determined by the logical address possessed by the command of the host CPU is introduced. A command processing section 34 prepares memory blocks and sectors for writing or erasing and copying at all times preparatory to the command processing of the host CPU and records and holds the corresponding relation of the physical addresses of the selected memory block 32i or sectors and the commands of the host CPU on an address conversion table 36. The conditions of the memory blocks and sectors are recorded on a management table 35 and are utilized for control of processing, such as writing, erasing and copying preparatory to or in response with the commands of the host CPU.

公开(公告)号：DE69223287T2

公开(公告)日：1998-05-28

申请号：DE69223287

申请日：1992-07-01

Applicant: IBM

Inventor： SAKAUE YOSHINORI ,  NIIJIMA HIDETO

IPC: G06F3/08 ,  G06F3/06 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/12 ,  G11C16/02 ,  G11C16/10 ,  G11C16/34 ,  G11C17/00

Abstract: To provide an external storage system using a semiconductor memory in which the data reading and writing between the host CPU can be processed faster than the conventional magnetic disk, and only a particular sector is not frequently written and erased so that the whole memory is effectively used over a long period of time, an address control scheme is introduced in which flexibility is given to the address relation between the host CPU and the external storage and the physical address of the semiconductor memory is not one-sidedly determined by the logical address possessed by the command of the host CPU.