中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

2 records (took 0.016 seconds)

    DATA TRANSFER METHOD BETWEEN BUSES, BRIDGE DEVICE FOR CONNECTING BUSES TO EACH OTHER AND DATA PROCESSING SYSTEM INCLUDING PLURAL BUSES
    1.
    发明专利
    DATA TRANSFER METHOD BETWEEN BUSES, BRIDGE DEVICE FOR CONNECTING BUSES TO EACH OTHER AND DATA PROCESSING SYSTEM INCLUDING PLURAL BUSES 失效

    公开(公告)号：JPH10222457A

    公开(公告)日：1998-08-21

    申请号：JP1577297

    申请日：1997-01-29

    Applicant: IBM

    Inventor： KAMIJO KOICHI ,  SHO IKUO ,  HANAMI HIDENOBU

    IPC: G06F13/12 ,  G06F13/14 ,  G06F13/36

    Abstract: PROBLEM TO BE SOLVED: To control data transfer between buses, to mutually connect the buses and to transfer data between the buses by preserving the address of an access request destination in a self retry register and terminating a bus cycle on a secondary side PCI bus not by a target abort but by retry. SOLUTION: A PCI to PCI bridge 21 temporarily terminates the bus cycle not by target abort but by retry on the secondary side PCI bus 40 operating as a target. A secondary side PCI to ISA bridge 51 executes assertion and requests the bus cycle at subtractive timing. Thus, a transaction is transmitted to a secondary side ISA device 52 being a target and data is transferred between the master secondary side PCI device 42 and the slave secondary side ISA device 52 without fail.

    COMPUTER SYSTEM AND JUDGMENT METHOD OF CACHE HIT
    2.
    发明专利
    COMPUTER SYSTEM AND JUDGMENT METHOD OF CACHE HIT 失效

    公开(公告)号：JPH0895863A

    公开(公告)日：1996-04-12

    申请号：JP22161494

    申请日：1994-09-16

    Applicant: IBM

    Inventor： OBA NOBUYUKI ,  NAKADA TAKEO ,  SHO IKUO

    IPC: G06F12/08

    Abstract: PURPOSE: To provide a method for maintaining consistency of cache in a system which has 1st physical memory and 2nd physical memory that is common with at least a part of physical addresses of all of physical addresses of the 1st physical memory, selects the 1st physical memory/2nd physical memory by its operation mode and accesses. CONSTITUTION: Flag bit 23 is provided as a means which stores information that specifies data source in tag memory 20 of cache. Then, the cache decides cache hit/miss based on not only a fact that the data relating to an CPU request address exists in the cache, but also considers the information on an operation mode which is simultaneoulsy sent from the CPU and also decides whether data source whose data the CPU requests coincides with data source whose data is stored in the cache. The cache hit is not decided until these two conditions are matched with each other.

Patent Agency Ranking