公开(公告)号：WO0195382A3

公开(公告)日：2002-08-29

申请号：PCT/US0118539

申请日：2001-06-07

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CLEVENGER LAWRENCE A ,  HSU LOUIS ,  STEPHENS JEREMY K ,  WISE MICHAEL

IPC: H01L21/76 ,  H01L21/285 ,  H01L21/304 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L21/31053 ,  H01L21/28525 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/7684

Abstract: A method of using diamond or a diamond-like carbon layer as a polish-stop for patterning a metal level into an inter-level dielectric substrate using a damascene process flow. The diamond or diamond-like carbon layer is deposited onto the surface of the substrate before patterning the metal level. A protective layer is then deposited over the diamond or diamond-like carbon polish-stop layer, wherein such protective layer may act as an additional polish-stop layer. Together, the diamond or diamond-like carbon polish-stop layer and the protective layer are used as a hard-mask for patterning the trenches that will become the metal features, wherein such protective layer protects the diamond or diamond-like carbon polish-stop layer during the patterning process. After deposition of a conductive metal layer, the dielectric substrate is polished to remove excess conductive material, as well as topography. In the polishing process, the diamond or diamond-like carbon polish-stop layer and any remaining protective layer are used as polish-stop layers. The diamond or diamond-like carbon polish-stop layer allows for an improved planar surface, thereby resulting in an sufficient decrease in topography at the surface of the inter-level dielectric.

Abstract translation: 使用金刚石或类金刚石碳层作为抛光停止件的方法，其使用镶嵌工艺流程将金属层图案化成层间电介质基板。 在图案化金属层之前，将金刚石或类金刚石碳层沉积在基板的表面上。 然后将保护层沉积在金刚石或类金刚石碳抛光层上，其中这种保护层可以用作另外的抛光停止层。 一起使用金刚石或类金刚石碳抛光层和保护层作为用于图案化将成为金属特征的沟槽的硬掩模，其中这种保护层保护金刚石或类金刚石碳抛光 在图案化过程中。 在沉积导电金属层之后，电介质基底被抛光以除去过量的导电材料以及形貌。 在抛光过程中，将金刚石或类金刚石碳抛光层和任何剩余的保护层用作抛光 - 停止层。 金刚石或类金刚石碳抛光层允许改进的平面表面，从而导致层间电介质表面的形貌的充分降低。

公开(公告)号：JP2003030987A

公开(公告)日：2003-01-31

申请号：JP2002142731

申请日：2002-05-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： FIFIELD JOHN A ,  STORASKA DANIEL W ,  WIN K RUK ,  STEPHENS JEREMY K ,  KIRIHATA TOSHIAKI

IPC: G11C11/409 ,  G11C7/06 ,  G11C11/4091

CPC classification number: G11C7/067 ,  G11C7/062 ,  G11C11/4091

Abstract: PROBLEM TO BE SOLVED: To provide a memory architecture, in which coupling noise between bit lines is small at CMOS intersection coupling sensing operation, and which operates at a high speed.
SOLUTION: In a single bit-line direct sensing architecture, a sense amplifier circuit, having four transistors arranged for each memory array, is used. In this circuit, the transistor functions so that a data bit from a true bit-line of a pair of bit line or an auxiliary bit line is transferred selective to a data line. The data line is preferably arranged on a plurality of memory arrays, and the data line may not be required, to share in read operation and write operation. Furthermore, digital sensing scheme function is performed, by charging a data line during read-out operation using one more current source detecting the ratio of a current source, driving by a bit line of a corresponding array and resistance of a transistor.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种存储架构，其中位线之间的耦合噪声在CMOS交叉耦合感测操作处较小，并且以高速运行。 解决方案：在单个位线直接感测架构中，使用具有为每个存储器阵列布置的四个晶体管的读出放大器电路。 在该电路中，晶体管起作用，使得来自一对位线或辅助位线的真位置的数据位被选择性地传送到数据线。 数据线优选地布置在多个存储器阵列上，并且可能不需要数据线，以共享读操作和写操作。 此外，通过使用检测电流源的比例的一个电流源，通过相应阵列的位线驱动和晶体管的电阻来驱动读出操作期间的数据线，执行数字感测方案功能。

公开(公告)号：JP2002076003A

公开(公告)日：2002-03-15

申请号：JP2001171139

申请日：2001-06-06

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  HSU LOUIS L C ,  STEPHENS JEREMY K ,  WISE MICHAEL

IPC: H01L21/76 ,  H01L21/285 ,  H01L21/304 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/762 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a topography extremely reduced on a semiconductor surface formed by a damascene process. SOLUTION: A diamond or diamond like carbon film is adhered to the surface of a substrate as a polishing stop layer before a metal level pattern is formed. Next, a protective film is adhered on the diamond or diamond like carbon polishing stop layer. The protective film can be used as another polishing stop layer. Both the diamond or diamond like carbon film and the protective film are used as a hard mask so that a pattern is formed in a trench that has metallic features. The protective film protects the diamond or diamond like carbon polishing stop layer during a pattern forming process. After a conductive metal layer is adhered, the substrate is polished, and redundant conducting materials and the topography are removed.

公开(公告)号：JPH11288906A

公开(公告)日：1999-10-19

申请号：JP5923599

申请日：1999-03-05

Applicant: SIEMENS AG ,  IBM

Inventor： WISE MICHAEL L ,  STEPHENS JEREMY K ,  HEDGE SURI G

IPC: H01L21/304 ,  B24B37/30 ,  B24B49/14 ,  H01L21/3105 ,  H01L21/321

Abstract: PROBLEM TO BE SOLVED: To reduce or remove the nonuniformity in polishing speed between chemical and mechanical polishing(CMP) methods, by providing a device which raises the with temperature of the first part of a semiconductor wafer with respect to the temperature of a second part of the semiconductor wafer. SOLUTION: A part of a wafer carrier 15 is heated up or cooled down by a temperature controller. Annular heating tapes 18 and 19 are attached to the back side 16 of the carrier 15 to perform local heating. When the heating tapes 18 and 19 are activated, heat is conducted through a wafer carrier 15, and imparts different heatings to the wafer wafer. Accordingly for example, the part 10a of the wafer 10 is cooler than the adjacent part 10b which is affected by the heating tape 19. The part 10b is relatively hot, when it is compared with the adjacent part 10a which is not affected by the heating tapes 18 and 19. The part 10b is maintained at a temperature higher than these of the parts 10c and 10e by receiving the affection of the heating tape 18.

公开(公告)号：DE60132435T2

公开(公告)日：2008-07-31

申请号：DE60132435

申请日：2001-03-12

Applicant: IBM ,  QIMONDA AG

Inventor： CLEVENGER LARRY ,  HSU LOUIS L ,  NARAYAN CHANDRASEKHAR ,  STEPHENS JEREMY K ,  WISE MICHAEL

IPC: H01L23/525 ,  H01L21/768

Abstract: An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further electrically insulating layer over the at least one electrically insulating layer. The electrically insulating layer(s) have a depression formed over the portion substantially free of electrical wiring, with the depression having a lower surface level than an adjacent portion of the electrically insulating layer. The fuse structure also includes a fuse insulator disposed over the depression and a fuse over the fuse insulator. Preferably, the fuse insulator is disposed only in the depression to elevate the fuse to the same level as the adjacent portion of the electrically insulating layer. The fuse structure may have a single layer or comprise alternating layers having different degrees of reflectivity to a laser beam, such as alternating layers of silicon oxide and silicon nitride. The preferred fuse structure comprises an electrically and thermally resistive fuse insulator in the depression, such that the fuse insulator substantially prevents heat of an energy beam directed at the fuse from being transmitted to the semiconductor substrate. More preferably, the fuse formed has a width less that that of the fuse insulator. The fuse structure may further include additional wiring over the electrical insulating layer at the same level as the fuse.

公开(公告)号：DE69935291T2

公开(公告)日：2007-11-22

申请号：DE69935291

申请日：1999-07-30

Applicant: SIEMENS AG ,  IBM

Inventor： BOGGS KARL E ,  LIN CHENTING ,  NEUTZEL JOACHIM F ,  PLOESSL ROBERT ,  RONAY MARIA ,  SCHNABEL FLORIAN ,  STEPHENS JEREMY K

IPC: H01L21/304 ,  H01L21/3105 ,  B24B37/013 ,  B24B49/12 ,  H01L21/306 ,  H01L21/66 ,  H01L23/544

Abstract: The method of polishing metal layers on wafers comprises the steps of: using a chemical-mechanical polisher (50) to polish the metal layers (32) to remove material therefrom, inspecting indicator areas on the wafer to determine an amount of material removed from said areas (80), and adjusting the operation of the chemical-mechanical polisher (50) in response to the inspection of the indicator areas (80). The indicator areas (80) may include macroblocks comprised of a multitude of individual blocks (82). The wafer may be inspected by optically identifying the polishing state of the blocks (82) in the macroblock (80). Additionally, the process may be automated for mass production. A feedback loop to the polisher can be formed where data from optical inspection of macroblocks on a polished wafer can be immediately fed back to the polisher in order to adjust process parameters.

公开(公告)号：DE60132435D1

公开(公告)日：2008-03-06

申请号：DE60132435

申请日：2001-03-12

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CLEVENGER LARRY ,  HSU LOUIS L ,  NARAYAN CHANDRASEKHAR ,  STEPHENS JEREMY K ,  WISE MICHAEL

IPC: H01L23/525 ,  H01L21/768

Abstract: An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further electrically insulating layer over the at least one electrically insulating layer. The electrically insulating layer(s) have a depression formed over the portion substantially free of electrical wiring, with the depression having a lower surface level than an adjacent portion of the electrically insulating layer. The fuse structure also includes a fuse insulator disposed over the depression and a fuse over the fuse insulator. Preferably, the fuse insulator is disposed only in the depression to elevate the fuse to the same level as the adjacent portion of the electrically insulating layer. The fuse structure may have a single layer or comprise alternating layers having different degrees of reflectivity to a laser beam, such as alternating layers of silicon oxide and silicon nitride. The preferred fuse structure comprises an electrically and thermally resistive fuse insulator in the depression, such that the fuse insulator substantially prevents heat of an energy beam directed at the fuse from being transmitted to the semiconductor substrate. More preferably, the fuse formed has a width less that that of the fuse insulator. The fuse structure may further include additional wiring over the electrical insulating layer at the same level as the fuse.

公开(公告)号：DE69935291D1

公开(公告)日：2007-04-12

申请号：DE69935291

申请日：1999-07-30

Applicant: SIEMENS AG ,  IBM

Inventor： BOGGS KARL E ,  LIN CHENTING ,  NEUTZEL JOACHIM F ,  PLOESSL ROBERT ,  RONAY MARIA ,  SCHNABEL FLORIAN ,  STEPHENS JEREMY K

IPC: H01L21/304 ,  H01L21/3105 ,  B24B37/013 ,  B24B49/12 ,  H01L21/306 ,  H01L21/66 ,  H01L23/544

Abstract: The method of polishing metal layers on wafers comprises the steps of: using a chemical-mechanical polisher (50) to polish the metal layers (32) to remove material therefrom, inspecting indicator areas on the wafer to determine an amount of material removed from said areas (80), and adjusting the operation of the chemical-mechanical polisher (50) in response to the inspection of the indicator areas (80). The indicator areas (80) may include macroblocks comprised of a multitude of individual blocks (82). The wafer may be inspected by optically identifying the polishing state of the blocks (82) in the macroblock (80). Additionally, the process may be automated for mass production. A feedback loop to the polisher can be formed where data from optical inspection of macroblocks on a polished wafer can be immediately fed back to the polisher in order to adjust process parameters.