公开(公告)号：EP1911096A4

公开(公告)日：2008-10-22

申请号：EP06788341

申请日：2006-07-24

Applicant: IBM

Inventor： DALTON TIMOTHY J ,  HSU LOUIS L C ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO ,  GAIDIS MICHAEL C ,  RADENS CARL ,  CLEVENGER LAWRENCE A

IPC: H01L27/22 ,  H01L21/768 ,  H01L21/8247 ,  H01L23/528 ,  H01L43/12

CPC classification number: B82Y10/00 ,  H01L27/222 ,  H01L43/12

Abstract: A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.

公开(公告)号：EP1994563A4

公开(公告)日：2011-06-22

申请号：EP07797080

申请日：2007-01-16

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS C ,  RADENS CARL ,  WONG KWONG-HON ,  YANG CHIH-CHAO

IPC: H01L27/01 ,  H01L21/8234

CPC classification number: H01L27/1203 ,  H01L21/28114 ,  H01L21/823456 ,  H01L21/84 ,  H01L29/42376 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2140458A4

公开(公告)日：2010-05-05

申请号：EP07867608

申请日：2007-12-04

Applicant: IBM

Inventor： GAIDIS MICHAEL C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  DEBROSSE JOHN K ,  HSU LOUIS L C ,  RADENS CARL ,  WONG KEITH K H ,  YANG CHIH-CHAO

IPC: G11C19/08 ,  G11B5/008

CPC classification number: G11C19/0841 ,  B82Y10/00 ,  G11C5/02 ,  G11C11/161 ,  G11C11/1675 ,  Y10T29/53165

公开(公告)号：EP2235744A4

公开(公告)日：2011-12-14

申请号：EP09704513

申请日：2009-01-15

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  DORIS BRUCE B ,  HUANG ELBERT E ,  PURUSHOTHAMAN SAMPATH ,  RADENS CARL J

IPC: H01L29/78 ,  H01L21/311 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

公开(公告)号：EP1875499A4

公开(公告)日：2009-11-04

申请号：EP06749449

申请日：2006-04-07

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS C

IPC: H01L21/8242 ,  H01L21/20

CPC classification number: H01L23/5223 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1920493A4

公开(公告)日：2011-05-04

申请号：EP06802645

申请日：2006-08-30

Applicant: IBM

Inventor： HSU LOUIS C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  RADENS CARL J ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

IPC: H01H50/00 ,  H01P1/10

CPC classification number: H01H50/005 ,  H01H2050/007 ,  Y10T29/4902 ,  Y10T29/49105 ,  Y10T29/49147

公开(公告)号：EP1869700A4

公开(公告)日：2010-12-15

申请号：EP06740771

申请日：2006-04-07

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  CLEVENGER LAWRENCE A ,  COWLEY ANDREW P ,  DALTON TIMOTHY J ,  YOON MEEYOUNG H

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76849 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1836726A4

公开(公告)日：2010-07-28

申请号：EP05852629

申请日：2005-12-02

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS C ,  RADENS CARL J ,  STANDAERT THEODORUS E ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

IPC: H01L21/4763

CPC classification number: H01L21/76852 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：WO2007016047A3

公开(公告)日：2008-01-03

申请号：PCT/US2006028718

申请日：2006-07-24

Applicant: IBM ,  GAIDIS MICHAEL C ,  RADENS CARL ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS L C ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

Inventor： GAIDIS MICHAEL C ,  RADENS CARL ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS L C ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: B82Y10/00 ,  H01L27/222 ,  H01L43/12

Abstract: A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.

Abstract translation: 磁性随机存取存储器（MRAM）器件包括形成在下布线层上的磁隧道结（MTJ）堆叠，形成在MTJ堆叠上的硬掩模和形成在硬掩模上的上布线层。 上布线层包括经由位于其中的位线的槽，槽经由与硬掩模接触的位线并与部分地围绕硬掩模的侧壁的蚀刻停止层接触。

公开(公告)号：WO2011032741A3

公开(公告)日：2012-04-05

申请号：PCT/EP2010059849

申请日：2010-07-09

Applicant: IBM ,  KRAUSE RAINER KLAUS ,  LI ZHENGWEN O ,  QUON ROGER A ,  CLEVENGER LAWRENCE A ,  PETRARCA KEVIN S ,  RADENS CARL ,  SAPP BRIAN C

Inventor： KRAUSE RAINER KLAUS ,  LI ZHENGWEN O ,  QUON ROGER A ,  CLEVENGER LAWRENCE A ,  PETRARCA KEVIN S ,  RADENS CARL ,  SAPP BRIAN C

IPC: H01L31/05 ,  H05K1/02 ,  H05K3/22

CPC classification number: H01L31/042 ,  H01L31/0465 ,  H01L31/0504 ,  H02S50/10 ,  Y02E10/50

Abstract: The invention relates to a method for manufacturing a thin-film photovoltaic cell module (10) encompassing an array of cells (100), comprising the steps of (i) providing the array of cells (100); (ii) determining, per cell (100), an electrical performance for one or more cells (100) of the array; (iii) identifying each cell (100) by its position in the array; (iv) determining one or more electrical paths (50, 52, 54) encompassing one or more of the cells (100) according to at least one optimization criterion; and (v) combining two or more cells (100) for realizing one or more electrical paths (50, 52, 54) by maintaining or establishing electrical connections (30) between individual cells (100) of the array according to the at least one optimization criterion.

Abstract translation: 本发明涉及一种用于制造包围电池阵列（100）的薄膜光伏电池模块（10）的方法，包括以下步骤：（i）提供电池阵列（100）; （ii）每个单元（100）确定阵列的一个或多个单元（100）的电性能; （iii）通过其在阵列中的位置来识别每个单元（100）; （iv）根据至少一个优化标准确定包含一个或多个所述单元（100）的一个或多个电路径（50,52,54）; 以及（v）通过根据所述至少一个维持或建立阵列的各个单元（100）之间的电连接（30），组合用于实现一个或多个电路径（50,52,54）的两个或更多个单元（100） 优化标准。