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    Dram and its refresh method
    3.
    发明专利
    Dram and its refresh method 审中-公开
    DRAM及其更新方法

    公开(公告)号：JP2003346477A

    公开(公告)日：2003-12-05

    申请号：JP2002153219

    申请日：2002-05-28

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： SUNANAGA TOSHIO ,  WATANABE SHINPEI ,  MORI MASAYA

    IPC: G11C11/406

    CPC classification number: G11C11/406 ,  G11C2211/4061 ,  G11C2211/4067

    Abstract: PROBLEM TO BE SOLVED: To provide a DRAM low in power consumption and low in manufacturing cost without needing an SRAM, and to provide a refresh method.
    SOLUTION: This DRAM 10 comprises terminals 18a, 18b to which addresses of memory blocks 16a, 16b, 16c, 16d are inputted, selectors 20a, 20b, 20c, 20d selecting T/C of addresses, and a circuit selecting a block from signal of T or C of an address outputted from the selectors 20a, 20b, 20c, 20d.
    COPYRIGHT: (C)2004,JPO

    Abstract translation: 要解决的问题：提供功耗低且制造成本低的DRAM而不需要SRAM，并提供刷新方法。 解决方案：该DRAM10包括输入存储块16a，16b，16c，16d的地址的端子18a，18b，选择地址的T / C的选择器20a，20b，20c，20d，以及选择块 从选择器20a，20b，20c，20d输出的地址的T或C信号。 版权所有（C）2004，JPO

    Memory cell, storage circuit block, data write-in method, and data read-out method
    4.
    发明专利
    Memory cell, storage circuit block, data write-in method, and data read-out method 有权
    存储单元，存储电路块，数据写入方法和数据读出方法

    公开(公告)号：JP2003016776A

    公开(公告)日：2003-01-17

    申请号：JP2001193984

    申请日：2001-06-27

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： MIYATAKE HISATADA ,  SUNANAGA TOSHIO ,  KITAMURA TSUNEJI

    IPC: G11C11/14 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

    Abstract: PROBLEM TO BE SOLVED: To provide a memory cell, a storage circuit block, and a data write-n method in which a current value made to flow in a bit line at the time of write-in of data is reduced, further, to provide a memory cell, a storage circuit block, and a data read-out method in which parasitic resistance of a switching element or the like at the time of read-out of data is reduced. SOLUTION: The MRAM 10 comprises a second switching element connecting first wiring structure 18 and an adjacent memory cell 12 in a memory cell 12, and second wiring structure body 20. Also, a third switching element is provided between the second wiring structure body 20 and ground.

    Abstract translation: 要解决的问题：提供一种存储单元，存储电路块和数据写入方法，其中在数据写入时在位线中流动的当前值减小，此外，为了 提供存储单元，存储电路块和数据读出方法，其中在读出数据时开关元件等的寄生电阻减小。 解决方案：MRAM 10包括将第一布线结构18和相邻的存储单元12连接在存储单元12中的第二开关元件和第二布线结构体20.另外，第三开关元件设置在第二布线结构体20和 地面。

    DATA INPUT/OUTPUT METHOD, AND DRAM
    6.
    发明专利
    DATA INPUT/OUTPUT METHOD, AND DRAM 审中-公开

    公开(公告)号：JP2002358783A

    公开(公告)日：2002-12-13

    申请号：JP2001199439

    申请日：2001-06-29

    Applicant: IBM

    Inventor： SUNANAGA TOSHIO ,  WATANABE SHINPEI

    IPC: G11C11/407 ,  G11C11/409

    Abstract: PROBLEM TO BE SOLVED: To provide a data input/output method which can minimize losses of data interruption at the time of switching between reading and writing in a DRAM using a common input/output section for reading and writing data, and to provide a DRAM. SOLUTION: This data input/output method comprises a step for holding predetermined data from a memory array 12 by a read command of m-th (m is integer), a step for outputting the data to a common input/output section 30 and holding new data from the memory array 12 upon (m+1)-th read command, a step for holding the data from the common input/output section 30 upon n-th (n is integer) write command, and a step for storing the data in the memory array 12 and holding new data from the common input/output section 30 upon (n+1)-th write command.

    BICMOS LOGICAL CIRQUIT
    7.
    发明专利
    BICMOS LOGICAL CIRQUIT 失效

    公开(公告)号：JPH03283816A

    公开(公告)日：1991-12-13

    申请号：JP7906690

    申请日：1990-03-29

    Applicant: IBM

    Inventor： SUNANAGA TOSHIO

    IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L29/732 ,  H03K17/567 ,  H03K19/017 ,  H03K19/08 ,  H03K19/0944

    Abstract: PURPOSE: To obtain high-speed switching by performing base charge discharging operation by diode-connected P-channel FET(field-effect transistor) and N- channel FET. CONSTITUTION: When an input varies from a low level to a high level, an FET(T) 4 turns on and T1 turns off, so that the voltage at a node N2 drops. In the beginning, T2 turns on strongly, so base charges of a transistor Q1 are drawn out through T2. As the voltage at the node N2 further drops, the substrate bias effect of T3 becomes small and the substrate bias effect of T2 becomes large to the contrary, so that T3 draws base charges out strongly. The drawn-out base charges are discharged to a ground voltage (GND) through T4. Therefore, a discharge path which efficiently draws the base charges out is formed. Consequently, high-speed switching operation can be obtained.

    Semiconductor storage device
    8.
    发明专利
    Semiconductor storage device 有权

    公开(公告)号：JP2004047002A

    公开(公告)日：2004-02-12

    申请号：JP2002205149

    申请日：2002-07-15

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： SUNANAGA TOSHIO

    IPC: G11C11/401 ,  G11C11/407

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor storage device in which seamless data can be inputted and outputted even if interruption occurs during a burst operation.
    SOLUTION: A plurality of segment arrays #0 to #15 that are independently activated from one another are provided. Each of the segment arrays includes a plurality of unit arrays that are independently activated from one another. Each of the segment arrays is provided with a prefetch latch circuit for latching burst read data and a preload latch circuit for latching burst write data. Even if there is interruption during a burst operation of a unit array UARY 1 in a certain segment array #14, a unit array UARY 2 in another activated segment array #3 starts a burst operation.
    COPYRIGHT: (C)2004,JPO

    Storage circuit block and data write-in method
    9.
    发明专利
    Storage circuit block and data write-in method 有权
    存储电路块和数据写入方法

    公开(公告)号：JP2003016774A

    公开(公告)日：2003-01-17

    申请号：JP2001194227

    申请日：2001-06-27

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： MIYATAKE HISATADA ,  NODA HIROYOSHI ,  UMEZAKI HIROSHI ,  ASANO HIDEO ,  SUNANAGA TOSHIO ,  KITAMURA TSUNEJI

    IPC: G11C11/14 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

    Abstract: PROBLEM TO BE SOLVED: To solve such a problem that because a current is required to make to flow for each bit line when data are written simultaneously in a plurality of data bits belonging to the same column address, a current required for write-in is enlarged.
    SOLUTION: This device comprises a plurality of pairs of bit line comprising a first bit line and a second bit line, a plurality of storage cells storing information in accordance with the direction of a current flowing in the pair of bit line, at least one current driving source connected to at least one of pairs of bit line and making to flow a current in the first bit line and the second bit line of which the directions of current are reverse each other, at least one switch circuit connecting pairs of bit line and pairs of bit line, and a control circuit controlling a connection state of the switch circuit in accordance with information stored in the storage cell.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题：为了解决由于在属于同一列地址的多个数据位中同时写入数据时需要为每个位线流动电流的问题，写入所需的电流为 放大 解决方案：该装置包括多对位线，包括第一位线和第二位线，多个存储单元根据在一对位线中流动的电流的方向存储信息，至少一个电流 驱动源连接到位线对中的至少一个并使得流过第一位线中的电流，并且使电流方向彼此相反的第二位线，至少一个连接成对的位线和 一对位线，以及根据存储在存储单元中的信息来控制开关电路的连接状态的控制电路。

    NONVOLATILE MAGNETIC MEMORY CELL HAVING MULTILAYER STRUCTURE AND STORAGE CIRCUIT BLOCK USING THE SAME
    10.
    发明专利
    NONVOLATILE MAGNETIC MEMORY CELL HAVING MULTILAYER STRUCTURE AND STORAGE CIRCUIT BLOCK USING THE SAME 失效

    公开(公告)号：JP2002359355A

    公开(公告)日：2002-12-13

    申请号：JP2001159353

    申请日：2001-05-28

    Applicant: IBM

    Inventor： KITAMURA TSUNEJI ,  SUNANAGA TOSHIO ,  MIYATAKE HISATADA

    IPC: G11C11/14 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

    Abstract: PROBLEM TO BE SOLVED: To provide a nonvolatile magnetic memory cell having a multilayer structure and a storage circuit block using the same. SOLUTION: A nonvolatile magnetic memory cell 40 is constituted to include a second bit line 38b, a second storage device 10b which is connected to the second bit line 38b and includes a ferroelectric layer of which magnetization direction is changed by a direction of a magnetic field generated by an electric current that flows in the second bit line 38b, a second switching device 30b of which one end is connected to a third wiring structure 24, and a second wiring structure 22b which sandwiches the second storage device 10b with the second bit line 38b and allows the second storage device 10b and the other end of the second switching device 30b to connect to each other.

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