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    Memory cell, storage circuit block, data write-in method, and data read-out method
    1.
    发明专利
    Memory cell, storage circuit block, data write-in method, and data read-out method 有权
    存储单元，存储电路块，数据写入方法和数据读出方法

    公开(公告)号：JP2003016776A

    公开(公告)日：2003-01-17

    申请号：JP2001193984

    申请日：2001-06-27

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： MIYATAKE HISATADA ,  SUNANAGA TOSHIO ,  KITAMURA TSUNEJI

    IPC: G11C11/14 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

    Abstract: PROBLEM TO BE SOLVED: To provide a memory cell, a storage circuit block, and a data write-n method in which a current value made to flow in a bit line at the time of write-in of data is reduced, further, to provide a memory cell, a storage circuit block, and a data read-out method in which parasitic resistance of a switching element or the like at the time of read-out of data is reduced. SOLUTION: The MRAM 10 comprises a second switching element connecting first wiring structure 18 and an adjacent memory cell 12 in a memory cell 12, and second wiring structure body 20. Also, a third switching element is provided between the second wiring structure body 20 and ground.

    Abstract translation: 要解决的问题：提供一种存储单元，存储电路块和数据写入方法，其中在数据写入时在位线中流动的当前值减小，此外，为了 提供存储单元，存储电路块和数据读出方法，其中在读出数据时开关元件等的寄生电阻减小。 解决方案：MRAM 10包括将第一布线结构18和相邻的存储单元12连接在存储单元12中的第二开关元件和第二布线结构体20.另外，第三开关元件设置在第二布线结构体20和 地面。

    Memory cell, storage circuit block, data write method and data read method
    6.
    发明专利
    Memory cell, storage circuit block, data write method and data read method 审中-公开
    存储单元，存储电路块，数据写入方法和数据读取方法

    公开(公告)号：JP2002368196A

    公开(公告)日：2002-12-20

    申请号：JP2001161718

    申请日：2001-05-30

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： MIYATAKE HISATADA ,  SUNANAGA TOSHIO ,  KITAMURA TSUNEJI

    IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

    CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/16

    Abstract: PROBLEM TO BE SOLVED: To provide a memory cell, a storage circuit block, a data write method and data read method in which production yield is high, cost is low, reliability is high, and the chip area can be reduced by reducing the number of metal wiring layers. SOLUTION: A memory cell 12 is configured so as to include metal lines 16 intersecting with bit liens 14 in a no-contact manner therewith, and a second wiring structure 24 for connecting the lines 16 to switching elements 20. A write circuit 26 for making a current flow through the lines 16 and a ground 28 are connected to the lines 16 via a switch 30 for selecting the circuit 26 and the ground 28.

    Abstract translation: 要解决的问题：为了提供一种存储单元，存储电路块，数据写入方法和数据读取方法，其中生产率高，成本低，可靠性高，并且可以通过减少数量来减少芯片面积 的金属布线层。 解决方案：存储单元12被配置为包括与位留置体14以不接触的方式相交的金属线16，以及用于将线16连接到开关元件20的第二布线结构24.用于制造的写入电路26 通过线16和地线28的电流通过用于选择电路26和地面28的开关30连接到线路16。

    Storage circuit block and data write-in method
    7.
    发明专利
    Storage circuit block and data write-in method 有权
    存储电路块和数据写入方法

    公开(公告)号：JP2003016774A

    公开(公告)日：2003-01-17

    申请号：JP2001194227

    申请日：2001-06-27

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： MIYATAKE HISATADA ,  NODA HIROYOSHI ,  UMEZAKI HIROSHI ,  ASANO HIDEO ,  SUNANAGA TOSHIO ,  KITAMURA TSUNEJI

    IPC: G11C11/14 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

    Abstract: PROBLEM TO BE SOLVED: To solve such a problem that because a current is required to make to flow for each bit line when data are written simultaneously in a plurality of data bits belonging to the same column address, a current required for write-in is enlarged.
    SOLUTION: This device comprises a plurality of pairs of bit line comprising a first bit line and a second bit line, a plurality of storage cells storing information in accordance with the direction of a current flowing in the pair of bit line, at least one current driving source connected to at least one of pairs of bit line and making to flow a current in the first bit line and the second bit line of which the directions of current are reverse each other, at least one switch circuit connecting pairs of bit line and pairs of bit line, and a control circuit controlling a connection state of the switch circuit in accordance with information stored in the storage cell.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题：为了解决由于在属于同一列地址的多个数据位中同时写入数据时需要为每个位线流动电流的问题，写入所需的电流为 放大 解决方案：该装置包括多对位线，包括第一位线和第二位线，多个存储单元根据在一对位线中流动的电流的方向存储信息，至少一个电流 驱动源连接到位线对中的至少一个并使得流过第一位线中的电流，并且使电流方向彼此相反的第二位线，至少一个连接成对的位线和 一对位线，以及根据存储在存储单元中的信息来控制开关电路的连接状态的控制电路。

    NONVOLATILE MAGNETIC MEMORY CELL HAVING MULTILAYER STRUCTURE AND STORAGE CIRCUIT BLOCK USING THE SAME
    8.
    发明专利
    NONVOLATILE MAGNETIC MEMORY CELL HAVING MULTILAYER STRUCTURE AND STORAGE CIRCUIT BLOCK USING THE SAME 失效

    公开(公告)号：JP2002359355A

    公开(公告)日：2002-12-13

    申请号：JP2001159353

    申请日：2001-05-28

    Applicant: IBM

    Inventor： KITAMURA TSUNEJI ,  SUNANAGA TOSHIO ,  MIYATAKE HISATADA

    IPC: G11C11/14 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

    Abstract: PROBLEM TO BE SOLVED: To provide a nonvolatile magnetic memory cell having a multilayer structure and a storage circuit block using the same. SOLUTION: A nonvolatile magnetic memory cell 40 is constituted to include a second bit line 38b, a second storage device 10b which is connected to the second bit line 38b and includes a ferroelectric layer of which magnetization direction is changed by a direction of a magnetic field generated by an electric current that flows in the second bit line 38b, a second switching device 30b of which one end is connected to a third wiring structure 24, and a second wiring structure 22b which sandwiches the second storage device 10b with the second bit line 38b and allows the second storage device 10b and the other end of the second switching device 30b to connect to each other.

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