-
公开(公告)号：GB2587948A
公开(公告)日：2021-04-14
申请号：GB202017634
申请日：2019-04-02
Applicant: IBM
Inventor： JAMES O'CONNOR , BARRY TRAGER , WARREN MAULE , MARC GOLLUB , BRAD WILLIAM MICHAEL , PATRICK JAMES MEANEY
IPC: G11C16/26
Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. Each of the memory devices are characterized as one of a high random bit error rate (RBER) and a low RBER memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices. The memory buffer device also includes common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The common error correction logic includes a plurality of error correction units which provide different complexity levels of error correction and have different latencies. The error correction units include a first fast path error correction unit for isolating and correcting random symbol errors.
-
公开(公告)号：GB2585514B
公开(公告)日：2021-05-19
申请号：GB202012499
申请日：2019-01-15
Applicant: IBM
Inventor： KEVIN MCILVAIN , STEPHEN GLANCY , WARREN MAULE , KYU-HYOUN KIM
Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.
-
公开(公告)号：GB2587948B
公开(公告)日：2021-11-24
申请号：GB202017634
申请日：2019-04-02
Applicant: IBM
Inventor： JAMES O'CONNOR , BARRY TRAGER , WARREN MAULE , MARC GOLLUB , BRAD WILLIAM MICHAEL , PATRICK JAMES MEANEY
Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. Each of the memory devices are characterized as one of a high random bit error rate (RBER) and a low RBER memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices. The memory buffer device also includes common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The common error correction logic includes a plurality of error correction units which provide different complexity levels of error correction and have different latencies. The error correction units include a first fast path error correction unit for isolating and correcting random symbol errors.
-
公开(公告)号：GB2585514A
公开(公告)日：2021-01-13
申请号：GB202012499
申请日：2019-01-15
Applicant: IBM
Inventor： KEVIN MCILVAIN , STEPHEN GLANCY , WARREN MAULE , KYU-HYOUN KIM
Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.
-
-
-
Search Results
4
records
(took 0.015 seconds)
