公开(公告)号：DE3176699D1

公开(公告)日：1988-05-05

申请号：DE3176699

申请日：1981-08-19

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  KOTECHA HARISH NARANDAS ,  WIEDMAN FRANCIS WALTER

IPC: H01L27/112 ,  G11C14/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/00

Abstract: This invention provides improved non-volatile semiconductor memories which include a volatile circuit (10) coupled to a non-volatile device (22) having a floating gate (28) and first and second control gates (34, 36 & 38, 40) capacitively coupled to the floating gate (28) with a charge injector structure (40) disposed between the floating gate and one of the two control gates. The volatile circuit may be a dynamic one-device cell such as a conventional flip-flop or latch cell.

公开(公告)号：DE3377690D1

公开(公告)日：1988-09-15

申请号：DE3377690

申请日：1983-05-06

Applicant: IBM

Inventor： KALTER HOWARD LEO ,  WIEDMAN FRANCIS WALTER

IPC: G06F7/00 ,  G06F7/50 ,  G06F7/505 ,  H03K19/096 ,  H03K19/177