公开(公告)号：DE3166342D1

公开(公告)日：1984-10-31

申请号：DE3166342

申请日：1981-10-05

Applicant: IBM

Inventor： KOTECHA HARISH NARANDAS ,  NOBLE JR ,  WIEDMAN III FRANCIS WALTER

IPC: H01L27/112 ,  G11C16/04 ,  G11C17/00 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

公开(公告)号：DE3781336D1

公开(公告)日：1992-10-01

申请号：DE3781336

申请日：1987-06-05

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  KOTECHA HARISH NARANDAS

IPC: G11C14/00 ,  G11C11/41 ,  G11C11/56 ,  G11C17/14

公开(公告)号：DE3176835D1

公开(公告)日：1988-09-08

申请号：DE3176835

申请日：1981-04-28

Applicant: IBM

Inventor： KOTECHA HARISH NARANDAS

IPC: H01L27/112 ,  G11C16/04 ,  G11C17/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34 ,  H01L29/60

公开(公告)号：AU540886B2

公开(公告)日：1984-12-06

申请号：AU7007581

申请日：1981-05-01

Applicant: IBM

Inventor： KOTECHA HARISH NARANDAS

IPC: H01L27/112 ,  G11C16/04 ,  G11C17/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40 ,  H01L27/08 ,  H01L29/76

公开(公告)号：DE3781336T2

公开(公告)日：1993-04-01

申请号：DE3781336

申请日：1987-06-05

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  KOTECHA HARISH NARANDAS

IPC: G11C14/00 ,  G11C11/41 ,  G11C11/56 ,  G11C17/14

公开(公告)号：DE3174565D1

公开(公告)日：1986-06-12

申请号：DE3174565

申请日：1981-08-19

Applicant: IBM

Inventor： KOTECHA HARISH NARANDAS

IPC: G11C14/00 ,  H01L27/115 ,  H01L29/788 ,  G11C11/00

Abstract: This invention provides improved non-volatile semiconductor memories which include a volatile latch circuit having data nodes (A, B) and first and second cross-coupled transistors (12, 14), at least one of the transistors has first and second control gates (30,46; 42, 56), a floating gate (24) and an enhanced conduction insulator (48) or dual electron injector structure disposed between the first control gate (30, 46) and the floating gate (24). The second control gate (42, 56) is connected to the storage node (A). A control voltage source (20, 22) is connected to the first control gate (30, 46) for transferring charge between the enhanced conduction insulator or dual electron injector structure (48) and the data node.

公开(公告)号：DE3172114D1

公开(公告)日：1985-10-10

申请号：DE3172114

申请日：1981-05-19

Applicant: IBM

Inventor： KOTECHA HARISH NARANDAS ,  WIEDMAN FRANCIS WALTER III

IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

公开(公告)号：DE3475845D1

公开(公告)日：1989-02-02

申请号：DE3475845

申请日：1984-08-08

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  KOTECHA HARISH NARANDAS

IPC: G11C16/04 ,  G11C11/56 ,  G11C17/12 ,  G11C17/00

公开(公告)号：DE3176699D1

公开(公告)日：1988-05-05

申请号：DE3176699

申请日：1981-08-19

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  KOTECHA HARISH NARANDAS ,  WIEDMAN FRANCIS WALTER

IPC: H01L27/112 ,  G11C14/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/00

Abstract: This invention provides improved non-volatile semiconductor memories which include a volatile circuit (10) coupled to a non-volatile device (22) having a floating gate (28) and first and second control gates (34, 36 & 38, 40) capacitively coupled to the floating gate (28) with a charge injector structure (40) disposed between the floating gate and one of the two control gates. The volatile circuit may be a dynamic one-device cell such as a conventional flip-flop or latch cell.

公开(公告)号：DE3170944D1

公开(公告)日：1985-07-18

申请号：DE3170944

申请日：1981-10-09

Applicant: IBM

Inventor： KALTER HOWARD LEO ,  KOTECHA HARISH NARANDAS ,  PATEL PARSOTAM TRIKAM

IPC: H01L27/112 ,  G11C14/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/00

Abstract: The non-volatile semiconductor memory includes a one device dynamic volatile memory cell having a storage capacitor (C5) with a plate (12) and a storage node (10) coupled to a non-volatile device having a floating gate (FG), a control gate (24) and a voltage divider (16) having first and second serially-connected capacitors (C1, C2), with the floating gate (FG) being disposed at the common point between the first and second capacitors. The plate (12) of the storage capacitor is connected to a reference voltage source. The control gate (24) is preferably capacitively coupled to the floating gate (FG) through the first (C1) capacitor which includes a dual charge or electron injector structure (26). The capacitance of the first capacitor (C1) has a value substantially less than that of the second capacitor (C2).