公开(公告)号：US6444490B2

公开(公告)日：2002-09-03

申请号：US89470601

申请日：2001-06-28

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  FERENCE THOMAS GEORGE ,  HOWELL WAYNE JOHN ,  FIFIELD JOHN ATKINSON

IPC: H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H05K1/02 ,  H01L21/44

CPC classification number: H01L23/49816 ,  H01L23/49524 ,  H01L23/49531 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06579 ,  H01L2924/00013 ,  H01L2924/01079 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0228 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of the chip at increased frequencies.

Abstract translation: 公开了薄膜微纤维双绞线对和其它连接器。 半导体封装包括将至少一个芯片电连接到另一层封装的微技术技术。 根据本发明的诸如薄膜双绞线对连接器的Microflex连接器提供优异的电气性能，其包括降低的线路电感，集成的无源部件的结合以及将离散的被动和有源部件附接到微反射镜。 所有这些特性使芯片在频率增加的情况下能够运行。

公开(公告)号：US6410431B2

公开(公告)日：2002-06-25

申请号：US74653400

申请日：2000-12-19

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  HOWELL WAYNE JOHN ,  TONTI WILLIAM R ,  ZALESINSKI JERZY MARIA

IPC: H01L23/13 ,  H01L23/367 ,  H01L23/48 ,  H01L21/44

CPC classification number: H01L23/13 ,  H01L23/3677 ,  H01L23/481 ,  H01L2223/6622 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2924/19104 ,  H01L2924/00014

Abstract: Through-chip conductors for low inductance chip-to-chip integration and off-chip connections in a semiconductor package is disclosed. A semiconductor device has active devices on the front surface, a first through-chip conductor having first electrical/physical characteristics passing from the front surface of the device to the back surface, a second through-chip conductor having second electrical/physical characteristics passing to the back surface, and an off-chip or chip-to-chip connector electrically connecting the active devices on the front surface to a different level of packaging.

Abstract translation: 公开了用于半导体封装中的低电感芯片到芯片集成和片外连接的芯片导体。 半导体器件在前表面上具有有源器件，具有从器件的前表面到后表面的第一电/物理特性的第一贯通芯片导体，具有第二电/物理特性的第二贯通芯片导体， 后表面，以及将前表面上的有源器件电连接到不同级别的封装的芯片外或芯片到芯片连接器。

公开(公告)号：JP2004201499A

公开(公告)日：2004-07-15

申请号：JP2004037233

申请日：2004-02-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BERTIN CLAUDE LOUIS ,  CRONIN JOHN EDWARD

IPC: B81B5/00 ,  B81B7/00 ,  B81C1/00 ,  B81C3/00 ,  H01H1/00 ,  H01L21/306 ,  H01L29/84 ,  H01L49/00 ,  H02N1/00

CPC classification number: H01H1/0036 ,  H02N1/004

Abstract: PROBLEM TO BE SOLVED: To provide a machine and a method of production, making work useful for considerably larger degree than that executed by micromachine technology. SOLUTION: A machine structure respectively, including a plurality of micromachine layers stacked on each other, and its making method are presented. Each machine structure includes a movable member, demarcated from a micro-structure of at least one layer of a plurality of the micro-machine layers, including stacks. In the case of manufacture, VLSI technique is used, the micro-machine layer is formed separately thereafter stacked on each other in an arrangement by a form of the stack, the machine structure is demarcated. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2002319674A

公开(公告)日：2002-10-31

申请号：JP2002035743

申请日：2002-02-13

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  DALLY ANTHONY J ,  FIFIELD JOHN ATKINSON ,  HIGGINS JOHN JESSE ,  MANDELMAN JACK ALLAN ,  TONTI WILLIAM R ,  HEEL NICHOLAS MARTIN VAN

IPC: H01L21/225 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/82 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor equipped having a dielectric layer of two-dimensional thickness, and to provide a method of manufacturing the same. SOLUTION: This manufacturing method comprises a first process of forming a mask with a through-hole 20 equipped with a side wall 21 on a structure (a), a second process of implanting suppression chemical seeds 24 into the structure through the through-hole 20 so as to form a suppression region 26 in the structure (b), and a third process of enabling a dielectric layer 28 to grow on the structure in the through-hole 20. Here, the suppression region 26 restrains the dielectric layer 28 partially from growing. By this setup, a self-aligned MOSFET or an anti-fuse device having a low overlap capacitance and a low gate induction drain leakage (i.e., low electric field) can be formed.

公开(公告)号：JPH0883888A

公开(公告)日：1996-03-26

申请号：JP20688195

申请日：1995-08-14

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  HOWELL WAYNE JOHN ,  BEILSTEIN KENNETH EDWARD JR ,  DAUBENSPECK TIMOTHY HARRISON

IPC: H01L25/18 ,  H01L21/02 ,  H01L21/301 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/98 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L27/00 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a technique of selectively removing a material, which is used at the time of forming an electronic module, constituted of a 'stack' of a plurality of chips, from a cut groove region (kerf region) related to the semiconductor chips. SOLUTION: This method includes a method of providing a wafer having a plurality of integrated circuit chips having a cut groove region 17 between them. Chip metallized films 15 and 16 exist in the region 17. The wafer is protected using a photolithographic process, and only the region 17 is exposed. Then, the wafer is etched, and the chip metallized films are removed from the region 17. Then the wafer is diced, and the chips are stacked to form a monolithic electronic module. The side surfaces of the module are treated to expose a transfer metallic film which extends to the side surfaces of the module. Thereby, the electrical connection of the transfer metallic film to the chips in the module is facilitated.

公开(公告)号：DE3781336T2

公开(公告)日：1993-04-01

申请号：DE3781336

申请日：1987-06-05

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  KOTECHA HARISH NARANDAS

IPC: G11C14/00 ,  G11C11/41 ,  G11C11/56 ,  G11C17/14

公开(公告)号：DE69218076T2

公开(公告)日：1997-09-18

申请号：DE69218076

申请日：1992-08-10

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  FARRAR PAUL ALDEN ,  KALTER HOWARD LEO ,  KELLEY GORDON ARTHUR ,  VAN DER HOEVEN WILLEM BERNARD ,  WHITE FRANCIS ROGER

IPC: H01L27/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

Abstract: A fabrication method and resultant three-dimensional multichip package having a densely stacked array of semiconductor chips interconnected at least partially by means of a plurality of metallized trenches are disclosed. The fabrication method includes providing an integrated circuit chip (50) having high aspect ratio metallized trenches (62) therein extending from a first surface to a second surface (58) thereof. An etch stop layer is provided proximate the termination position of the metallized trenches with the semiconductor substrate (52). Next the integrated circuit device is affixed to a carrier (70) such that the surface of the supporting substrate is exposed and substrate is thinned from the integrated circuit device until exposing at least some of the plurality of metallized trenches therein. Electrical contact can thus be made to the active layer of the integrated circuit chip via the exposed metallized trenches (66). Specific details of the fabrication method and the resultant multichip package are set forth.

公开(公告)号：DE3781336D1

公开(公告)日：1992-10-01

申请号：DE3781336

申请日：1987-06-05

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  KOTECHA HARISH NARANDAS

IPC: G11C14/00 ,  G11C11/41 ,  G11C11/56 ,  G11C17/14

公开(公告)号：DE2861099D1

公开(公告)日：1981-12-03

申请号：DE2861099

申请日：1978-12-05

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS

IPC: G11C11/412 ,  G11C7/20 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/04 ,  H01L27/11 ,  H01L29/43 ,  H03K3/356 ,  H01L29/62 ,  G11C11/40 ,  H01L27/10 ,  H03K3/353

Abstract: An improved bistable FET circuit is disclosed which employs a reduced number of device elements and occupies less space in an integrated circuit. The flip-flop circuit includes the FET device having its source connected to a first potential and a second FET device having its source also connected to the first potential. The first FET device has a gate electrode composed of a resistive material with the first side connected to the drain of the second FET device and the second side connected to a second potential. The second FET device has a gate electrode comprised of a resistive material with the first side connected to the drain of the first FET device and a second side connected to the second potential. In this manner, the resistive gate of the first device serves as the load for the second device and the resistive gate of the second device serves as the load for the first device. Application of this circuit to electrically programmable PLA's and to random access memories is disclosed.

公开(公告)号：DE69218076D1

公开(公告)日：1997-04-17

申请号：DE69218076

申请日：1992-08-10

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  FARRAR PAUL ALDEN ,  KALTER HOWARD LEO ,  KELLEY GORDON ARTHUR ,  VAN DER HOEVEN WILLEM BERNARD ,  WHITE FRANCIS ROGER

IPC: H01L27/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

Abstract: A fabrication method and resultant three-dimensional multichip package having a densely stacked array of semiconductor chips interconnected at least partially by means of a plurality of metallized trenches are disclosed. The fabrication method includes providing an integrated circuit chip (50) having high aspect ratio metallized trenches (62) therein extending from a first surface to a second surface (58) thereof. An etch stop layer is provided proximate the termination position of the metallized trenches with the semiconductor substrate (52). Next the integrated circuit device is affixed to a carrier (70) such that the surface of the supporting substrate is exposed and substrate is thinned from the integrated circuit device until exposing at least some of the plurality of metallized trenches therein. Electrical contact can thus be made to the active layer of the integrated circuit chip via the exposed metallized trenches (66). Specific details of the fabrication method and the resultant multichip package are set forth.