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公开(公告)号:JP2000188473A
公开(公告)日:2000-07-04
申请号:JP24210499
申请日:1999-08-27
Applicant: IBM
Inventor: LAUFFER JOHN M , VOYA R MARKOVICH , CHERIRU L PAROMAKI , WILLIAM E WILSON
IPC: H05K3/42 , C08L63/00 , C08L101/12 , C09D5/34 , C09D163/00 , H01B3/40 , H05K1/11 , H05K3/00 , H05K3/46
Abstract: PROBLEM TO BE SOLVED: To provide a method in which an opening in a substrate such as a through hole or the like is filled. SOLUTION: An epoxy resin-based dielectric film 16 which covers an opening 14 is arranged on a substrate 12 which comprises the opening 14. The dielectric film 16 is made to reflow so as to flow into the opening 14. A continuous dielectric which is extended into the opening 14 from the dielectric film 16 is formed. When a via 18 is formed after the opening 14 is filled, light is image-formed on the dielectric film 16, the via 18 is metallized, and a circuit structure 24 is formed. It is preferable that the dielectric film 16 contains 0 to 50% of inorganic fine particles, 50 to 100% of an epoxy resin and a cation photoinhibitor of 0.1 to 15 pts.wt. in terms of the total weight of the resin are contained.
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公开(公告)号:JP2000174435A
公开(公告)日:2000-06-23
申请号:JP30733399
申请日:1999-10-28
Applicant: IBM
Inventor: KENNETH FALLON , MAIGUERU A JIMAAZU , ROSS W KEITHLER , LAUFFER JOHN M , ROY H MAGNUSON , VOYA R MARKOVICH , AIRA MENISU , JIM P PAOLETTI , MAARIBESU PERINO , JOHN A WELSH , WILLIAM E WILSON
Abstract: PROBLEM TO BE SOLVED: To obtain a circuit card, in which layers made of dielectric material for exposure type latent image formation are used on both opposing surfaces of a metal layer forming a power plane. SOLUTION: This method is provided for forming a printed circuit card. A metal layer 20 which functions as a power plane is sandwiched by a pair of layers 24 and 26 of a photoimageable material, capable of forming a latent with use of a light beam. Photoformed metal-filled vias 46 and photoformed plating through-hole 48 are in a photopatternable material. A signal circuit is formed on the two dielectric layers to be connected to the vias 46 and a through-hole 48. The board has a border 14 in its periphery, and the metal layer 20 has an end which is apart from an end of one 26 of the dielectric layers.
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