公开(公告)号：JPH1056249A

公开(公告)日：1998-02-24

申请号：JP14758197

申请日：1997-06-05

Applicant: IBM

Inventor： LAUFFER JOHN M ,  PAPATHOMAS KONSTANTINOS

IPC: H05K1/16 ,  H05K3/42 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To obtain a printed circuit board having a decoupled ground bus and a power bus and an extremely large decoupling capacitor by laminating a first conductor foil coated, at least on one side thereof, with a dielectric material together with a second conductor foil on the coating of the dielectric material. SOLUTION: Copper sheets 10, 14 are punched according to a clearance hole pattern on the ground plane and a copper sheet 12 is punched according to a clearance hole pattern on the hot side ASM dry coating sheets 18, 20 are then pasted onto the upper and lower surfaces of the copper sheet 12 and an ASM dry coating sheets 22 is pasted onto the lower surface of the copper sheet 14. Subsequently, these copper sheet/ASM dry coating structures are laminated together with prefabricated cores 24, 26, glass cloths 36, 38 and outer copper foils 40, 42 to produce a composite multilayer board. The composite multilayer board is then punched and processed through plating and outer circuit are made, thus completing a board having four parallel capacitive planes 44, 46, 48, 50.

公开(公告)号：DE69715523T2

公开(公告)日：2003-05-28

申请号：DE69715523

申请日：1997-06-11

Applicant: IBM

Inventor： LAUFFER JOHN M ,  PAPATHOMAS KONSTANTINOS

IPC: H05K1/16 ,  H05K3/42 ,  H05K3/46

Abstract: A method is provided for producing a capacitor to be embedded in an electronic circuit package comprising the steps of selecting a first conductor foil, selecting a dielectric material, coating the dielectric material on at least one side of the first conductor foil, and layering the coated foil with a second conductor foil on top of the coating of dielectric material. Also claimed is an electronic circuit package incorporating at least one embedded capacitor manufactured in accordance with the present invention.

公开(公告)号：JP2000188473A

公开(公告)日：2000-07-04

申请号：JP24210499

申请日：1999-08-27

Applicant: IBM

Inventor： LAUFFER JOHN M ,  VOYA R MARKOVICH ,  CHERIRU L PAROMAKI ,  WILLIAM E WILSON

IPC: H05K3/42 ,  C08L63/00 ,  C08L101/12 ,  C09D5/34 ,  C09D163/00 ,  H01B3/40 ,  H05K1/11 ,  H05K3/00 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a method in which an opening in a substrate such as a through hole or the like is filled. SOLUTION: An epoxy resin-based dielectric film 16 which covers an opening 14 is arranged on a substrate 12 which comprises the opening 14. The dielectric film 16 is made to reflow so as to flow into the opening 14. A continuous dielectric which is extended into the opening 14 from the dielectric film 16 is formed. When a via 18 is formed after the opening 14 is filled, light is image-formed on the dielectric film 16, the via 18 is metallized, and a circuit structure 24 is formed. It is preferable that the dielectric film 16 contains 0 to 50% of inorganic fine particles, 50 to 100% of an epoxy resin and a cation photoinhibitor of 0.1 to 15 pts.wt. in terms of the total weight of the resin are contained.

公开(公告)号：JP2000174435A

公开(公告)日：2000-06-23

申请号：JP30733399

申请日：1999-10-28

Applicant: IBM

Inventor： KENNETH FALLON ,  MAIGUERU A JIMAAZU ,  ROSS W KEITHLER ,  LAUFFER JOHN M ,  ROY H MAGNUSON ,  VOYA R MARKOVICH ,  AIRA MENISU ,  JIM P PAOLETTI ,  MAARIBESU PERINO ,  JOHN A WELSH ,  WILLIAM E WILSON

IPC: H05K3/42 ,  H05K1/05 ,  H05K3/00 ,  H05K3/10 ,  H05K3/44

Abstract: PROBLEM TO BE SOLVED: To obtain a circuit card, in which layers made of dielectric material for exposure type latent image formation are used on both opposing surfaces of a metal layer forming a power plane. SOLUTION: This method is provided for forming a printed circuit card. A metal layer 20 which functions as a power plane is sandwiched by a pair of layers 24 and 26 of a photoimageable material, capable of forming a latent with use of a light beam. Photoformed metal-filled vias 46 and photoformed plating through-hole 48 are in a photopatternable material. A signal circuit is formed on the two dielectric layers to be connected to the vias 46 and a through-hole 48. The board has a border 14 in its periphery, and the metal layer 20 has an end which is apart from an end of one 26 of the dielectric layers.

公开(公告)号：JP2002314258A

公开(公告)日：2002-10-25

申请号：JP2002075801

申请日：2002-03-19

Applicant: IBM

Inventor： ANSTROM DONALD O ,  CHAMBERLIN BRUCE J ,  LAUFFER JOHN M ,  MARKOVICH VOYA R ,  THOMAS DAVID L

IPC: H01L23/538 ,  H05K1/02 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure for realizing close wiring, which can exhibit excellent electric characteristics, while satisfying system resistance requirements and characteristic impedance requirements in a printed circuit board applied product or in a chip carrier applied product. SOLUTION: For close wiring, wiring length is selected to enable use of an allowable 'short' wiring as close circuit lines, or short-length wiring lines are provided in a necessary region and switched to possible rough wiring lines of low-resistance. In order to ensure that the resistance of the longest wiring used will not exceed a predetermined maximum resistance, all the wirings are required to have sufficient sectional areas. Provision of a burial via enables change to a low-resistance wiring to form a dense wiring in the element region.

公开(公告)号：JP2002314253A

公开(公告)日：2002-10-25

申请号：JP2002060395

申请日：2002-03-06

Applicant: IBM

Inventor： JONES GERALD W ,  LAUFFER JOHN M ,  MARKOVICH VOYA R ,  MILLER THOMAS R ,  PAOLLETTI JAMES P ,  CONSTANTINOS I PAPATHOMAS ,  STACK JAMES R

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a method which is newly simplified for forming a multilayer printed wiring board structure having a z-axis interconnection. SOLUTION: For forming a multilayer printed wiring board 10, a plurality of separate layers 12, 14, 16, 18 are shown, and in this example, the board 10 is constituted of four layers in total. As is well known, each layer is originally composed of a dielectric material such as an organic board, and on both surfaces thereof, namely on surfaces 12a, 12b, 14a, 14b, 16a, 16b, 18a, 18b, a suitable circulating plating, namely a wire is provided. As is well known, this is selectively adhered by use of a mask, etc. Each of the layers 12, 14, 16, 18 has a thickness 't' suitably in the range of about 0.50 mm (about 20 mil) to about 2.54 mm (about 100 mil) in correspondence to a size of a hole or a via formed therein.

公开(公告)号：JP2000174441A

公开(公告)日：2000-06-23

申请号：JP30748199

申请日：1999-10-28

Applicant: IBM

Inventor： LAUFFER JOHN M ,  ROY H MAGNUSON ,  VOYA R MARKOVICH ,  JOHN A WELSH

IPC: H05K3/00 ,  H05K3/42 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To form a chip carrier having two voltage faces and at least two signal faces by exposing a first layer made of dielectric material attached to a first metal layer to form openings which pass through the first layer. SOLUTION: A first layer 10 made of dielectric material is attached to a first metal layer 12 and then the first layer 10 is exposed to form openings which pass through the first layer 10. Then, a second metal layer 16 is attached to the first layer 10 and holes larger than corresponding opening patterns of the first layer 10 are formed by etching in the first and the second metal layer 12, 16 in correspondence to each opening pattern and then an exposure pattern on the first layer 10 is developed. The openings formed in the first and the second metal layer are larger than those of the first layer 10. Then, a second and a third layer 32, 34 which are capable of light image formation are attached to the first and the second metal layer 12, 16 respectively and then are formed into light patterns and developed to form openings corresponding to each hole of the first layer 10 in the second and the third layer 32, 34. Then, the first and the second metal layer 12, 16 are formed with holes which are terminated at the metal layer in the lower layer. Parts of the surfaces of the second and the third dielectric material are exposed and holes are filled with plating or metal.

公开(公告)号：MY117854A

公开(公告)日：2004-08-30

申请号：MYPI9702207

申请日：1997-05-20

Applicant: IBM

Inventor： LAUFFER JOHN M ,  PAPATHOMAS KONSTANTINOS

IPC: H05K1/16 ,  H05K3/42 ,  H05K3/46

Abstract: A METHOD IS PROVIDED FOR PRODUCING A CAPACITOR(44-50,78-80) TO BE EMBEDDED IN AN ELECTRONIC CIRCUIT PACKAGE COMPRISING THE STEPS OF SELECTING A FIRST CONDUCTOR FOIL, SELECTING A DIELECTRIC MATERIAL, COATING THE DIELECTRIC MATERIAL ON AT LEAST ONE SIDE OF THE FIRST CONDUCTOR FOIL, AND LAYERING THE COATED FOIL WITH A SECOND CONDUCTOR FOIL ON TOP OF THE COATING OF DIELECTRIC MATERIAL. ALSO CLAIMED IS AN ELECTRONIC CIRCUIT PACKAGE INCORPORATING AT LEAST ONE EMBEDDED CAPACITOR MANUFACTURED IN ACCORDANCE WITH THE PRESENT INVENTION. (FIG.1)

公开(公告)号：DE69715523D1

公开(公告)日：2002-10-24

申请号：DE69715523

申请日：1997-06-11

Applicant: IBM

Inventor： LAUFFER JOHN M ,  PAPATHOMAS KONSTANTINOS

IPC: H05K1/16 ,  H05K3/42 ,  H05K3/46

Abstract: A method is provided for producing a capacitor to be embedded in an electronic circuit package comprising the steps of selecting a first conductor foil, selecting a dielectric material, coating the dielectric material on at least one side of the first conductor foil, and layering the coated foil with a second conductor foil on top of the coating of dielectric material. Also claimed is an electronic circuit package incorporating at least one embedded capacitor manufactured in accordance with the present invention.

公开(公告)号：HK1028866A1

公开(公告)日：2001-03-02

申请号：HK00106779

申请日：2000-10-25

Applicant: IBM

Inventor： LAUFFER JOHN M ,  MAGNUSON ROY H ,  MARKOVICH VOYA R ,  WELSH JOHN A

IPC: H05K3/00 ,  H05K3/42 ,  H05K3/46 ,  H05K

Abstract: A technique for forming an organic chip carrier or circuit board, having two voltage planes and at least two signal planes is provided which includes bonding a first layer of photolithographic dielectric material to a first metal layer and exposing the first layer of dielectric material to a pattern of radiation to provide at least one opening through the first layer of the dielectric material. A second metal layer is bonded to the first layer of photoimageable material on the opposite side from the first metal layer. Holes are etched in the first and second metal layers which correspond to and are larger than each of the patterns on said openings in the first layer of dielectric material. The exposed pattern on the first layer of dielectric material is then developed, with the openings in the first and second metal layers being larger than the corresponding developed opening in the first dielectric material. Second and third layers of photoimageable dielectric material are applied on the first and second metal layers, respectively and are photopatterned and developed to provide openings in each of the second and third layers of dielectric material some of which correspond to each of the holes in the first layer of dielectric material and the holes in the first and second metal layers, some of which terminate at the underlying metal layer. The exposed surfaces of both the second and third dielectric material, are circuitized and the holes plated or filled with metal.