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    Data acquisition and control system including dynamic interrupt capability
    1.
    发明授权
    Data acquisition and control system including dynamic interrupt capability 失效
    数据采集​​和控制系统包括动态中断能力

    公开(公告)号：US3905025A

    公开(公告)日：1975-09-09

    申请号：US46133774

    申请日：1974-04-16

    Applicant: IBM

    Inventor： DAVIS MICHAEL I ,  LOFFREDO JOHN M ,  WISE LARRY E ,  RICKARD PATRICK L

    IPC: G06F9/46 ,  G06F9/48 ,  G06F13/26 ,  G06F3/00

    CPC classification number: G06F9/4812 ,  G06F9/462 ,  G06F9/4818 ,  G06F13/26

    Abstract: This data acquisition and control system includes many features for enhancing real time response to external or internal conditions. One feature relates to the use of multiple processor control circuits which can be switched between active and inactive status for controlling the performance of processor operations as a function of the level of priority of received interrupt service requests. Another feature pertains to I/O devices attached to the processor. These I/O devices include means for retaining data dynamically allocable by the processor program for specifying assigned interrupt levels and/or for identifying the requisite servicing subroutine in the processor to permit rapid response when an interrupt service is granted. The devices monitor their own status and provide a summary bit to the processor identifying whether or not a status data interchange is required. Multiple masking allows the processor to select between masking all interrupts, interrupts from any source on one or more interrupt priority levels, interrupts from a particular device or devices, or any combination of these.

    Abstract translation: 该数据采集和控制系统包括许多功能，用于增强对外部或内部条件的实时响应。 一个特征涉及使用多个处理器控制电路，其可以在主动和非活动状态之间进行切换，以根据接收的中断服务请求的优先级来控制处理器操作的性能。 另一个特征涉及连接到处理器的I / O设备。 这些I / O设备包括用于保留由处理器程序动态分配的用于指定分配的中断级别的数据和/或用于在处理器中识别必需的服务子例程以允许在给予中断服务时的快速响应的装置。 设备监控自己的状态，并向处理器提供摘要位，识别是否需要状态数据交换。 多重屏蔽允许处理器在一个或多个中断优先级别的屏蔽所有中断，任何源的中断，特定设备或设备的中断或这些的任何组合之间进行选择。

    SUPERVISOR ADDRESS KEY CONTROL SYSTEM
    2.
    发明专利
    SUPERVISOR ADDRESS KEY CONTROL SYSTEM 未知

    公开(公告)号：CA1075823A

    公开(公告)日：1980-04-15

    申请号：CA275543

    申请日：1977-04-05

    Applicant: IBM

    Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I ,  HOOD ROBERT A ,  MCDERMOTT THOMAS S ,  WISE LARRY E

    IPC: G06F12/06 ,  G06F12/14 ,  G06F13/00

    Abstract: System mode controls for obtaining limited addressability for supervisor programming operations without disturbing a user address key currently contained in a user key register (UKR). The mode controls are provided by bits in a system register called a level status register (LSR), which include an APM bit, and a supervisor state bit. The largest supervisor addressability is obtained when both the APM and supervisor state bits are set on, which permits execution of a supervisor program which can access user data and programs. In more detail, each instruction fetch must be in the supervisor key area, identified by a predetermined supervisor key value which is not in the UKR, while each operand of the fetched supervisor instruction is accessed in the user key area identified by the current key in the UKR. The supervisor is not permitted to access any user area which does not have its key in the UKR. Thus, the supervisor can be prevented from having addressability over part or all of the main memory. However, if the APM bit is off while the supervisor bit is on, alI instruction and operand storage accesses can only be made in the supervisor key area, regardless of whether the supervisor key or user key is in the UKR. Hence no user area is accessible to the supervisor. But, if the supervisor bit is off, all instruction and operand accesses can only be made in the user area of the key in the UKR. Hence the supervisor programs cannot execute. BC9-76-011

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