公开(公告)号：US12299940B2

公开(公告)日：2025-05-13

申请号：US17854310

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Sreenivas Kothandaraman ,  Stephen Junkins ,  Srihari Pratapa ,  Prasoonkumar Surti

IPC: G06T9/00 ,  G06T1/20

Abstract: Interleaving of variable bitrate streams for GPU implementations is described. An example of an apparatus includes one or more processors including a graphic processor, the graphics processor including a super-compression encoder pipeline to provide variable width interleaved coding; and memory for storage of data, wherein the graphics processor is to perform parallel dictionary encoding on a bitstream of symbols one of multiple workgroups, the workgroup to employ a plurality of encoders to generate a plurality of token-streams of variable lengths; create a histogram including at least tokens from the plurality of token-streams for the workgroup to generate an optimized entropy code; entropy code each of the plurality of token-streams for the workgroup into an encoded bitstream; and variably interleave the encoded bitstreams to generate an interleaved bitstream and bookkeep a size of the interleaved bitstream.

公开(公告)号：US12288287B2

公开(公告)日：2025-04-29

申请号：US18436688

申请日：2024-02-08

Applicant: Intel Corporation

Inventor： Atsuo Kuwahara ,  Deepak S. Vembar ,  Chandrasekaran Sakthivel ,  Radhakrishnan Venkataraman ,  Brent E. Insko ,  Anupreet S. Kalra ,  Hugues Labbe ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall ,  Prasoonkumar Surti ,  Murali Ramadoss

IPC: G06T15/00 ,  G06F9/50 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.

公开(公告)号：US20250117356A1

公开(公告)日：2025-04-10

申请号：US18915492

申请日：2024-10-15

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Aravindh Anantaraman ,  Elmoustapha Ould-Ahmed-Vall ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Joydeep Ray ,  Lakshminarayanan Striramassarma ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Kamal Sinha ,  Arthur Hunter ,  Prasoonkumar Surti ,  David Puffer ,  James Valerio ,  Ankur N. Shah

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

Abstract: Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.

公开(公告)号：US12223682B2

公开(公告)日：2025-02-11

申请号：US17357038

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Stephen Junkins ,  Sreenivas Kothandaraman ,  Prasoonkumar Surti ,  Srihari Pratapa ,  William Hux ,  John Feit

IPC: G06T9/00 ,  G06T1/20 ,  G06T1/60

Abstract: Variable width interleaved coding for graphics processing is described. An example of an apparatus includes one or more processors including a graphic processor; and memory for storage of data including data for graphics processing, wherein the graphics processor includes an encoder pipeline to provide variable width interleaved coding and a decoder pipeline to decode the variable width interleaved coding, and wherein the encoder pipeline is to receive a plurality of bitstreams from workgroups; perform parallel entropy encoding on the bitstreams to generate a plurality of encoded bitstreams for each of the workgroups; perform variable interleaving of the bitstreams for each workgroup based at least in part on data requirements for decoding received from the decoder pipeline; and compact outputs for each of the workgroups into a contiguous stream of interleaved data.

公开(公告)号：US12223585B2

公开(公告)日：2025-02-11

申请号：US18376098

申请日：2023-10-03

Applicant: INTEL CORPORATION

Inventor： Karol Szerszen ,  Prasoonkumar Surti ,  Gabor Liktor ,  Karthik Vaidyanathan ,  Sven Woop

IPC: G06T15/00 ,  G06T1/20 ,  G06T15/06 ,  G06T15/08 ,  G06T17/10

Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.

公开(公告)号：US20240411717A1

公开(公告)日：2024-12-12

申请号：US18738785

申请日：2024-06-10

Applicant: Intel Corporation

Inventor： Altug Koker ,  Lakshminarayanan Striramassarma ,  Aravindh Anantaraman ,  Valentin Andrei ,  Abhishek R. Appu ,  Sean Coleman ,  Varghese George ,  Pattabhiraman K ,  Mike MacPherson ,  Subramaniam Maiyuran ,  ElMoustapha Ould-Ahmed-Vall ,  Vasanth Ranganathan ,  Joydeep Ray ,  Jayakrishna P S ,  Prasoonkumar Surti

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

Abstract: Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.

公开(公告)号：US12118756B2

公开(公告)日：2024-10-15

申请号：US17845039

申请日：2022-06-21

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Kiran C. Veernapu ,  Prasoonkumar Surti ,  Joydeep Ray ,  Altug Koker ,  Eric G. Liskay

IPC: G06T9/00

CPC classification number: G06T9/00

Abstract: A mechanism is described for facilitating smart compression/decompression schemes at computing devices. A method of embodiments, as described herein, includes unifying a first compression scheme relating to three-dimensional (3D) content and a second compression scheme relating to media content into a unified compression scheme to perform compression of one or more of the 3D content and the media content relating to a processor including a graphics processor.

公开(公告)号：US12108239B2

公开(公告)日：2024-10-01

申请号：US17816960

申请日：2022-08-02

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Travis T. Schluessler ,  Prasoonkumar Surti ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  James M. Holland ,  Jeffery S. Boles ,  Jonathan Kennedy ,  Louis Feng ,  Atsuo Kuwahara ,  Barnan Das ,  Narayan Biswal ,  Stanley J. Baran ,  Gokcen Cilingir ,  Nilesh V. Shah ,  Archie Sharma ,  Mayuresh M. Varerkar

IPC: G06T1/20 ,  G06F3/01 ,  G06T15/06 ,  G09B21/00 ,  H04R1/40 ,  H04R3/00 ,  H04S7/00

CPC classification number: H04S7/303 ,  G06F3/016 ,  G06T1/20 ,  G06T15/06 ,  G09B21/003 ,  G09B21/006 ,  G09B21/008 ,  H04R1/406 ,  H04R3/005 ,  H04S2400/11 ,  H04S2420/01

Abstract: Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.

公开(公告)号：US12100103B2

公开(公告)日：2024-09-24

申请号：US17390198

申请日：2021-07-30

Applicant: Intel Corporation

Inventor： Eric Hoekstra ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Subramaniam Maiyuran ,  Kalyan Bhiravabhatla

IPC: G06T17/10 ,  G06T1/20 ,  G06T15/00 ,  G06T19/20

CPC classification number: G06T17/10 ,  G06T1/20 ,  G06T19/20 ,  G06T15/005 ,  G06T2219/2004

Abstract: Methods, systems and apparatuses provide for graphics processor technology that generates attribute plane coefficients based on barycentric coefficients, wherein the attribute plane coefficients are generated on a per polygon basis, and interpolates one or more pixel attributes based on the attribute plane coefficients. In one example, the technology excludes the barycentric coefficients from one or more per pixel operations.

公开(公告)号：US20240256483A1

公开(公告)日：2024-08-01

申请号：US18415052

申请日：2024-01-17

Applicant: Intel Corporation

Inventor： Altug Koker ,  Varghese George ,  Aravindh Anantaraman ,  Valentin Andrei ,  Abhishek R. Appu ,  Niranjan Cooray ,  Nicolas Galoppo Von Borries ,  Mike MacPherson ,  Subramaniam Maiyuran ,  ElMoustapha Ould-Ahmed-Vall ,  David Puffer ,  Vasanth Ranganathan ,  Joydeep Ray ,  Ankur N. Shah ,  Lakshminarayanan Striramassarma ,  Prasoonkumar Surti ,  Saurabh Tangri

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Embodiments are generally directed to graphics processor data access and sharing. An embodiment of an apparatus includes a circuit element to produce a result in processing of an application; a load-store unit to receive the result and generate pre-fetch information for a cache utilizing the result; and a prefetch generator to produce prefetch addresses based at least in part on the pre-fetch information; wherein the load-store unit is to receive software assistance for prefetching, and wherein generation of the pre-fetch information is based at least in part on the software assistance.