公开(公告)号：US20240006285A1

公开(公告)日：2024-01-04

申请号：US17855662

申请日：2022-06-30

Applicant: The Intel Corporation

Inventor： Yi Yang ,  Suddhasattwa Nad ,  Xiaoying Guo ,  Jieying Kong ,  Ala Omer ,  Christy Sennavongsa ,  Wei Wei ,  Ao Wang

IPC: H01L23/498 ,  H01L23/14 ,  H01L21/48 ,  H05K1/11 ,  H05K3/40 ,  H05K3/22

CPC classification number: H01L23/49822 ,  H01L23/145 ,  H01L23/49866 ,  H01L21/4857 ,  H05K1/115 ,  H05K3/4038 ,  H05K3/22 ,  H01L2224/16227 ,  H01L24/16

Abstract: Substrate assemblies having adhesion promotor layers and related methods are disclosed. An example apparatus includes a substrate, a dielectric layer, a first copper layer between the substrate and the dielectric layer, and a film between the dielectric layer and the first copper layer. The film including silicon and nitrogen and being substantially free of hydrogen. A via in the dielectric layer is to provide access to the first copper layer. A portion of the first copper layer uncovered in the via, a wall of the via and the portion of the first copper layer to be substantially free of fluorine. A seed copper layer positioned on the dielectric layer. The via wall and the portion of the first copper layer. The seed copper layer and the first copper layer define an undercut at an interface between the seed copper layer and the first copper layer.

公开(公告)号：US20230402368A1

公开(公告)日：2023-12-14

申请号：US17837732

申请日：2022-06-10

Applicant: Intel Corporation

Inventor： Benjamin T. Duong ,  Brian P. Balch ,  Kristof Darmawikarta ,  Darko Grujicic ,  Suddhasattwa Nad ,  Xing Sun ,  Marcel A. Wall ,  Yi Yang

IPC: H01L23/522 ,  H01C7/00 ,  H01L49/02

CPC classification number: H01L23/5228 ,  H01L28/24 ,  H01L23/5226 ,  H01C7/006

Abstract: Techniques for thin-film resistors in vias are disclosed. In the illustrative embodiment, thin-film resistors are formed in through-glass vias of a glass substrate of an interposer. The thin-film resistors do not take up a significant amount of area on a layer of the interposer, as the thin-film resistor extends vertically through a via rather than horizontally on a layer of the interposer. The thin-film resistors may be used for any suitable purpose, such as power dissipation or voltage control, current control, as a pull-up or pull-down resistor, etc.

公开(公告)号：US20230395445A1

公开(公告)日：2023-12-07

申请号：US17833650

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Kristof Darmawikarta ,  Tarek A. Ibrahim ,  Jeremy D. Ecton ,  Brandon Christian Marin ,  Gang Duan ,  Suddhasattwa Nad ,  Yi Yang ,  Benjamin T. Duong ,  Junxin Wang ,  Sameer R. Paital

IPC: H01L23/15 ,  H01L23/498 ,  H01L21/48 ,  H05K1/03 ,  H05K3/40

CPC classification number: H01L23/15 ,  H01L23/49827 ,  H01L21/486 ,  H05K1/0306 ,  H05K3/4061

Abstract: In one embodiment, a substrate includes a glass core layer defining a plurality of holes between a first side of the glass core layer and a second side of the glass core layer opposite the first side and a conductive metal inside the holes of the glass core layer. The conductive metal electrically couples the first side of the glass core layer and the second side of the glass core layer. The substrate also includes a dielectric material between the conductive metal and the inside surfaces of the holes of the glass core layer.

公开(公告)号：US20170358129A1

公开(公告)日：2017-12-14

申请号：US15525023

申请日：2014-12-08

Applicant: Intel Corporation

Inventor： Feng Chen ,  Yi Yang ,  Xiaoming Chen

IPC: G06T15/80 ,  G06T1/20

CPC classification number: G06T15/80 ,  G06F9/30014 ,  G06F9/3861 ,  G06T1/20 ,  G06T15/005

Abstract: One or more system, apparatus, method, and computer readable media is described below for automated data type precision control capable of improving rendering quality on a graphics processor. Perceptible rendering quality is dependent at least in part on number format precision (e.g., FP16 or FP32) employed for shader program variables. In accordance with embodiments, shader variables implemented in lower precision data formats are tracked during shader compile to identify those that might trigger a floating point overflow and/or underflow exception. For shaders including one or more such variable, resources are provided to automatically monitor overflow and/or underflow exceptions during shader execution. In further embodiments, shader code is automatically re-generated based, at least in part, upon occurrences of such exceptions, and an increased number format precision specified for one or more of the tracked shader variables.

公开(公告)号：US20240006291A1

公开(公告)日：2024-01-04

申请号：US17855961

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Jeremy D. Ecton ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Jason Steill ,  Yi Yang ,  Marcel Arlan Wall

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/49894 ,  H01L23/49816

Abstract: A substrate package comprises a substrate comprised of buildup layers. The substrate package can further include a passivating layer connected to the substrate and including a pocketed region. The pocketed region can include a first portion thinner than a second portion extending from the first portion. The substrate package can further include a solder ball encapsulated within the pocketed region. Other systems, apparatuses and methods are described.

公开(公告)号：US20230420353A1

公开(公告)日：2023-12-28

申请号：US17848053

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Yi Yang ,  Jason Steill ,  Jieying Kong

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L23/49811 ,  H01L23/49894 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4864 ,  H01L2924/35121 ,  H01L24/16

Abstract: An electronic device package comprises a substrate with a first side and a second side opposite the first side; a first conductive feature on the first side and having a first surface; a first dielectric material in contact with the first surface, wherein the first dielectric material has a first composition comprising silicon and nitrogen; a second conductive feature on the second side of the substrate and having a second surface; and a second dielectric material in contact with the second surface, wherein the second dielectric material has a second composition different than the first composition, and wherein a surface roughness of the second surface is greater than a surface roughness of the first surface.

公开(公告)号：US20230085997A1

公开(公告)日：2023-03-23

申请号：US17483439

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Yi Yang ,  Eungnak Han ,  Suddhasattwa Nad ,  Marcel Wall

IPC: H05K3/38

Abstract: Methods and apparatus to improve adhesion between metals and dielectrics in circuit devices are disclosed. An apparatus includes a metal layer, a dielectric layer adjacent the metal layer, and a polymeric bonding layer at an interface between the metal layer and the dielectric layer. A polymer molecule in the polymeric bonding layer including an R1 group, an R2 group, and a polymer chain extending between the R1 group and the R2 group. The R1 group is different than the R2 group. The polymeric bonding layer is bonded to the metal layer via the R1 group. The polymeric bonding layer is bonded to the dielectric layer via the R2 group.

公开(公告)号：US20180174349A1

公开(公告)日：2018-06-21

申请号：US15118887

申请日：2014-06-30

Applicant: INTEL CORPORATION

Inventor： Yi Yang ,  Xiaoming Chen ,  Feng Chen ,  Yan Hao

IPC: G06T15/00 ,  G06T15/04 ,  G06T1/60 ,  G06T11/40

CPC classification number: G06T15/005 ,  G06T1/60 ,  G06T11/40 ,  G06T15/04 ,  G06T2200/04

Abstract: Methods and apparatus relating to an adaptive partition mechanism with arbitrary tile shape for tile based rendering GPU (Graphics Processing Unit) architecture are described. In an embodiment, the primitive intersection cost value for each atomic tile of an image are determined at least partially based on a vertex element size, a vertex shader length, and a number of the vertices of a primitive of the image. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240113046A1

公开(公告)日：2024-04-04

申请号：US17957257

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Jason Scott Steill ,  Shayan Kaviani ,  Srinivas Venkata Ramanuja Pietambaram ,  Suddhasattwa Nad ,  Benjamin Duong ,  Srinivasan Raman ,  Yi Yang

IPC: H01L23/62 ,  H01L21/48 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498 ,  H01L23/64

CPC classification number: H01L23/62 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/49894 ,  H01L23/642 ,  H01L23/645 ,  H01L23/647 ,  H01L24/24 ,  H01L2224/24145 ,  H01L2924/12036

Abstract: Various embodiments disclosed relate to embedded components in glass core layers for semiconductor assemblies. The present disclosure includes a semiconductor assembly with a glass core having one or more cavities and a component embedded into the glass core at the one or more cavities portion, the component at least partially embedded in the glass core, and a semiconductor die attached to the substrate.

公开(公告)号：US20240006299A1

公开(公告)日：2024-01-04

申请号：US17855568

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Jason Steill ,  Yi Yang ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Marcel Arlan Wall ,  Gang Duan ,  Jeremy D. Ecton

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49894 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49833 ,  H01L23/49822 ,  H01L21/4857

Abstract: Disclosed herein are microelectronics package architectures utilizing SiNx based surface finishes and methods of manufacturing the same. The microelectronics packages may include a core material, a first plurality of pads, and a silicon nitride layer. The first plurality of pads are attached to the core material. The silicon nitride layer is attached to the core material. The silicon nitride material defines respective openings to expose at least a portion of each of the first plurality of pads.