公开(公告)号：US20230334613A1

公开(公告)日：2023-10-19

申请号：US18340139

申请日：2023-06-23

Applicant: Intel Corporation

Inventor： Kenneth Daxer ,  Stephen H. Gunther ,  Michael N. Derr ,  Eric Samson

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60

Abstract: Described herein, in one embodiment, is a graphics processor comprising a plurality of dies integrated in a package, at least one die of the plurality of dies functionally heterogeneous relative to at least one other die of the plurality of dies and manufactured with a different process technology than the at least one other die.

公开(公告)号：US12079155B2

公开(公告)日：2024-09-03

申请号：US17428216

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Selvakumar Panneer ,  Saurabh Tangri ,  Ben Ashbaugh ,  Scott Janus ,  Abhishek Appu ,  Varghese George ,  Ravishankar Iyer ,  Nilesh Jain ,  Pattabhiraman K ,  Altug Koker ,  Mike MacPherson ,  Josh Mastronarde ,  Elmoustapha Ould-Ahmed-Vall ,  Jayakrishna P. S ,  Eric Samson

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

公开(公告)号：US20230297159A1

公开(公告)日：2023-09-21

申请号：US18185008

申请日：2023-03-16

Applicant: Intel Corporation

Inventor： Kenneth Daxer ,  Stephen H. Gunther ,  Michael N. Derr ,  Eric Samson

IPC: G06F1/3287 ,  G06F1/329

CPC classification number: G06F1/3287 ,  G06F1/329

Abstract: Described herein, in one embodiment, are techniques to facilitate the partial powerdown of sub-components of an execution unit or other graphics processing resource based on the workload to be executed. In another embodiment, granular dynamic voltage and frequency scaling is enabled in which the voltage and frequency of groups of processing resources within a graphics processor can be separately scaled.

公开(公告)号：US20240061582A1

公开(公告)日：2024-02-22

申请号：US17820356

申请日：2022-08-17

Applicant: Intel Corporation

Inventor： Marc Beuchat ,  Eric Samson ,  Josh Mastronarde

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0625 ,  G06F3/0655 ,  G06F3/0679

Abstract: Methods, systems and apparatuses provide for technology that detects an access to memory, wherein the memory is on a discrete graphics device that includes an accelerator, sets an idle hysteresis value of the memory to a first level if the access to the memory is associated with activity in the accelerator, and sets the idle hysteresis value of the memory to a second level if the access to the memory is not associated with the activity in the accelerator, wherein the second level is greater than the first level.

公开(公告)号：US11774919B2

公开(公告)日：2023-10-03

申请号：US17125768

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Suyoung Bang ,  Wootaek Lim ,  Eric Samson ,  Charles Augustine ,  Muhammad Khellah

IPC: G05B11/42 ,  G05B11/12 ,  G05F1/46

CPC classification number: G05B11/12 ,  G05F1/46

Abstract: A distributed and scalable all-digital LDO (D-DLDO) voltage regulator allowing rapid scaling across technology nodes. The distributed DLDO includes many tillable DLDO units regulating a single supply voltage with a shared power distribution network (PDN). The D-DLDO includes an all-digital proportional-integral-derivative (PID) controller that receives a first code indicative of a voltage behavior on a power supply rail. A droop detector is provided to compare the first code with a threshold to determine a droop event, wherein information about the droop event is provided to the PID controller, wherein the PID controller generates a second code according to the first code and the information about the droop event. The DLDO includes a plurality of power gates that receive the second code.

公开(公告)号：US11238557B2

公开(公告)日：2022-02-01

申请号：US16369608

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Eric Samson ,  Jaymin B. Jasoliya

IPC: G06F9/30 ,  G06T1/20 ,  G06F1/3296 ,  G06F1/3228 ,  G06F1/3234

Abstract: Described is an apparatus comprising a first circuitry and a second circuitry. The first circuitry may process a sequence of Graphics Processing Unit (GPU) commands including an instruction carrying a flag that indicates a workload characteristic corresponding with the sequence of GPU commands. The second circuitry may initiate a power-directed parameter adjustment based upon the flag.

公开(公告)号：US20210242872A1

公开(公告)日：2021-08-05

申请号：US17020667

申请日：2020-09-14

Applicant: Intel Corporation

Inventor： Suyoung Bang ,  Eric Samson ,  Wootaek Lim ,  Charles Augustine ,  Muhammad Khellah

IPC: H03L7/081 ,  G04F10/00 ,  H03L7/085

Abstract: An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code.

公开(公告)号：US11211935B2

公开(公告)日：2021-12-28

申请号：US17020667

申请日：2020-09-14

Applicant: Intel Corporation

Inventor： Suyoung Bang ,  Eric Samson ,  Wootaek Lim ,  Charles Augustine ,  Muhammad Khellah

IPC: H03L7/081 ,  G04F10/00 ,  H03L7/085

Abstract: An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code.

公开(公告)号：US20210240142A1

公开(公告)日：2021-08-05

申请号：US17125768

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Suyoung Bang ,  Wootaek Lim ,  Eric Samson ,  Charles Augustine ,  Muhammad Khellah

IPC: G05B11/42 ,  G05F1/46

Abstract: A distributed and scalable all-digital LDO (D-DLDO) voltage regulator allowing rapid scaling across technology nodes. The distributed DLDO includes many tillable DLDO units regulating a single supply voltage with a shared power distribution network (PDN). The D-DLDO includes an all-digital proportional-integral-derivative (PID) controller that receives a first code indicative of a voltage behavior on a power supply rail. A droop detector is provided to compare the first code with a threshold to determine a droop event, wherein information about the droop event is provided to the PID controller, wherein the PID controller generates a second code according to the first code and the information about the droop event. The DLDO includes a plurality of power gates that receive the second code.

公开(公告)号：US10784874B1

公开(公告)日：2020-09-22

申请号：US16783096

申请日：2020-02-05

Applicant: Intel Corporation

Inventor： Suyoung Bang ,  Eric Samson ,  Wootaek Lim ,  Charles Augustine ,  Muhammad Khellah

IPC: H03L7/02 ,  H03M1/30 ,  H03M1/38 ,  G04F10/00 ,  H03L7/081 ,  H03L7/085

Abstract: An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code.