-
公开(公告)号：US20140290983A1
公开(公告)日：2014-10-02
申请号：US13853303
申请日：2013-03-29
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
CPC classification number: H05K3/4647 , H05K1/0366 , H05K3/38
Abstract: Disclosed is a stacked multilayer structure, including a first circuit layer having bumps, a plastic film stacked on the first circuit layer to fill up the space among the bumps so as to form a co-plane, and a second circuit layer formed on the co-plane and connected to the first circuit layer. The plastic film includes a glass fiber layer which is embedded and not exposed. The adhesion between plastic film and the second circuit layer is greatly improved because the glass fiber layer of the plastic film filling up the space among the bumps is not deformed and exposed outwards. Therefore, the yield and reliability of the stacked multilayer structure is increased.
Abstract translation: 公开了一种堆叠的多层结构，包括具有凸起的第一电路层，堆叠在第一电路层上以填充凸块之间的空间以形成共面的塑料膜，以及形成在共面上的第二电路层 平面并连接到第一电路层。 该塑料膜包括嵌入并不暴露的玻璃纤维层。 由于填充凸块之间的空间的塑料膜的玻璃纤维层不会变形并向外露出，所以塑料膜与第二电路层之间的粘合性大大提高。 因此，层叠多层结构的成品率和可靠性提高。
-
公开(公告)号：US08941224B2
公开(公告)日：2015-01-27
申请号：US13853281
申请日：2013-03-29
Applicant: Kinsus Interconnect Technology Corp.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC: H01L23/06 , H01L23/498
CPC classification number: H01L23/49827 , H01L21/563 , H01L23/49861 , H01L23/49894 , H01L23/562 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/0002 , H01L2924/00
Abstract: A package structure includes a thin chip substrate, a stabilizing material layer, a chip and a filling material. A first circuit metal layer of the substrate is inlaid into a dielectric layer and a co-plane is defined by the first circuit metal layer and the dielectric layer and is exposed from the dielectric layer. The bonding pads of the substrate are on the co-plane, have a height higher than the co-plane and connected to the first circuit metal layer. The stabilizing material layer is provided on two sides of the co-plane to define a receiving space for accommodating the chip. The filling material is injected into the receiving space to fasten the pins of the chip securely with bonding pads. Since no plastic molding is required, a total thickness of the package structure and the cost is reduced. The stabilizing material layer prevents the substrate from warping and distortion.
Abstract translation: 封装结构包括薄片基板，稳定材料层，芯片和填充材料。 衬底的第一电路金属层嵌入电介质层中，并且由第一电路金属层和电介质层限定共面，并从电介质层露出。 衬底的接合焊盘在共面上，具有高于共面的高度并连接到第一电路金属层。 稳定材料层设置在共面的两侧，以限定用于容纳芯片的容纳空间。 将填充材料注入到接收空间中，用粘合垫牢固地固定芯片的销。 由于不需要塑料成型，所以包装结构的总厚度和成本降低。 稳定材料层防止基材翘曲和变形。
-
公开(公告)号：US20140291853A1
公开(公告)日：2014-10-02
申请号：US13853281
申请日：2013-03-29
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC: H01L23/498
CPC classification number: H01L23/49827 , H01L21/563 , H01L23/49861 , H01L23/49894 , H01L23/562 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/0002 , H01L2924/00
Abstract: A package structure includes a thin chip substrate, a stabilizing material layer, a chip and a filling material. A first circuit metal layer of the substrate is inlaid into a dielectric layer and a co-plane is defined by the first circuit metal layer and the dielectric layer and is exposed from the dielectric layer. The bonding pads of the substrate are on the co-plane, have a height higher than the co-plane and connected to the first circuit metal layer. The stabilizing material layer is provided on two sides of the co-plane to define a receiving space for accommodating the chip. The filling material is injected into the receiving space to fasten the pins of the chip securely with bonding pads. Since no plastic molding is required, a total thickness of the package structure and the cost is reduced. The stabilizing material layer prevents the substrate from warping and distortion.
Abstract translation: 封装结构包括薄片基板，稳定材料层，芯片和填充材料。 衬底的第一电路金属层嵌入电介质层中，并且由第一电路金属层和电介质层限定共面，并从电介质层露出。 衬底的接合焊盘在共面上，具有高于共面的高度并连接到第一电路金属层。 稳定材料层设置在共面的两侧，以限定用于容纳芯片的容纳空间。 将填充材料注入到接收空间中，用粘合垫牢固地固定芯片的销。 由于不需要塑料成型，所以包装结构的总厚度和成本降低。 稳定材料层防止基材翘曲和变形。
-
公开(公告)号：US08887386B2
公开(公告)日：2014-11-18
申请号：US13663333
申请日：2012-10-29
Applicant: Kinsus Interconnect Technology Corp.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC: H05K3/02
CPC classification number: H05K1/056 , H01L21/4857 , H01L21/486 , H01L23/13 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L2924/0002 , H05K1/0204 , H05K2201/029 , H05K2201/0323 , H05K2201/09054 , H05K2203/0323 , H05K2203/0384 , H05K2203/063 , Y10T29/49117 , Y10T29/49121 , Y10T29/49124 , Y10T29/49155 , Y10T29/49156 , H01L2924/00
Abstract: A method of manufacturing a chip support board structure which includes the steps of forming a metal substrate structure, forming a photo resist pattern, etching the metal substrate structure to form a paddle, removing the photo resist pattern, pressing an insulation layer against the paddle, polishing the insulation layer, forming a circuit layer and forming a solder resist is disclosed. The metal substrate structure is formed by sandwiching a block layer with two metal substrate layers, multilayer. The metal substrate structure is etched under control to an effective depth such that each paddle thus formed has the same shape and depth. Therefore, the method of the present invention can be widely applied to the general mass production processes to effectively solve the problems in the prior arts due to depth differences, such offset, position mismatch and peeling off in the chip support board.
Abstract translation: 一种制造芯片支撑板结构的方法，其包括以下步骤：形成金属基板结构，形成光致抗蚀剂图案，蚀刻金属基板结构以形成桨，去除光致抗蚀剂图案，将绝缘层压靠在桨上， 公开了抛光绝缘层，形成电路层和形成阻焊剂。 金属基板结构是通过将具有两个金属基底层的多层的阻挡层夹在中间而形成的。 在控制下将金属基底结构蚀刻到有效深度，使得如此形成的每个桨具有相同的形状和深度。 因此，本发明的方法可以广泛地应用于通常的批量生产过程，以有效地解决由于芯片支撑板中的深度差异，偏移，位置失配和剥离等现有技术的问题。
-
公开(公告)号：US20140116755A1
公开(公告)日：2014-05-01
申请号：US13663250
申请日：2012-10-29
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC: H05K1/02
CPC classification number: H05K1/0271 , H05K3/4682 , H05K2201/09136 , H05K2201/2018
Abstract: A laminate circuit board structure which includes a first circuit metal layer, a first insulation layer, at least one second circuit metal layer, at least one second insulation layer and a support frame is disclosed. The total thickness of the laminate circuit board structure is less than 150 μm. The support frame provided at the outer edge of the co-plane surface formed by the first circuit metal layer and the first insulation layer does not cover the first circuit metal layer, and is formed of at least one metal material. The support frame provides physical support for the entire board structure without influence on the circuit connection so as to prevent the laminate circuit board structure from warping.
Abstract translation: 公开了一种层叠电路板结构，其包括第一电路金属层，第一绝缘层，至少一个第二电路金属层，至少一个第二绝缘层和支撑框架。 叠层电路板结构的总厚度小于150μm。 设置在由第一电路金属层和第一绝缘层形成的共面的外边缘处的支撑框架不覆盖第一电路金属层，并且由至少一种金属材料形成。 支撑框架为整个板结构提供物理支撑，而不影响电路连接，从而防止层压电路板结构翘曲。
-
Patent Agency Ranking
公开(公告)号：US20140115888A1
公开(公告)日：2014-05-01
申请号：US13663333
申请日：2012-10-29
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC: H05K3/06
CPC classification number: H05K1/056 , H01L21/4857 , H01L21/486 , H01L23/13 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L2924/0002 , H05K1/0204 , H05K2201/029 , H05K2201/0323 , H05K2201/09054 , H05K2203/0323 , H05K2203/0384 , H05K2203/063 , Y10T29/49117 , Y10T29/49121 , Y10T29/49124 , Y10T29/49155 , Y10T29/49156 , H01L2924/00
Abstract: A method of manufacturing a chip support board structure which includes the steps of forming a metal substrate structure, forming a photo resist pattern, etching the metal substrate structure to form a paddle, removing the photo resist pattern, pressing an insulation layer against the paddle, polishing the insulation layer, forming a circuit layer and forming a solder resist is disclosed. The metal substrate structure is formed by sandwiching a block layer with two metal substrate layers, multilayer. The metal substrate structure is etched under control to an effective depth such that each paddle thus formed has the same shape and depth. Therefore, the method of the present invention can be widely applied to the general mass production processes to effectively solve the problems in the prior arts due to depth differences, such offset, position mismatch and peeling off in the chip support board.
Abstract translation: 一种制造芯片支撑板结构的方法，其包括以下步骤：形成金属基板结构，形成光致抗蚀剂图案，蚀刻金属基板结构以形成桨，去除光致抗蚀剂图案，将绝缘层压靠在桨上， 公开了抛光绝缘层，形成电路层和形成阻焊剂。 金属基板结构是通过将具有两个金属基底层的多层的阻挡层夹在中间而形成的。 在控制下将金属基底结构蚀刻到有效深度，使得如此形成的每个桨具有相同的形状和深度。 因此，本发明的方法可以广泛地应用于通常的批量生产过程，以有效地解决由于芯片支撑板中的深度差异，偏移，位置失配和剥离等现有技术的问题。
-
公开(公告)号：US09095084B2
公开(公告)日：2015-07-28
申请号：US13853303
申请日：2013-03-29
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
CPC classification number: H05K3/4647 , H05K1/0366 , H05K3/38
Abstract: A stacked multilayer structure, including a first circuit layer having bumps, a plastic film stacked on the first circuit layer to fill up the space among the bumps so as to form a co-plane, and a second circuit layer formed on the co-plane and connected to the first circuit layer. The plastic film includes a glass fiber layer which is embedded and not exposed.
Abstract translation: 一种堆叠多层结构，包括具有凸起的第一电路层，堆叠在第一电路层上以填充凸块之间的空间以形成共面的塑料膜，以及形成在共面上的第二电路层 并连接到第一电路层。 该塑料膜包括嵌入并不暴露的玻璃纤维层。
-
公开(公告)号：US20140295623A1
公开(公告)日：2014-10-02
申请号：US13853255
申请日：2013-03-29
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC: H01L21/56
CPC classification number: H01L21/4846 , H01L21/4853 , H01L21/563 , H01L21/6835 , H01L23/3121 , H01L23/49811 , H01L23/49816 , H01L23/562 , H01L2221/68345 , H01L2224/73204
Abstract: Disclosed is a method of packaging a chip and a substrate, including the steps of forming a substrate with a thickness ranging from 70 to 150 μm, which comprises a dielectric layer, a circuit metal layer stacked on the dielectric layer and bonding pads higher than the dielectric layer by 10 to 15 μm; forming a stabilizing structure around the substrate to provide a receiving space; disposing the chip on the receiving space and bonding the pins of the chip with the bonding pads; and filling up the receiving space under the chip with a filling material to a total thickness ranging from 300 to 850 μm. Without the plastic molding process, the present invention reduces the cost and the total thickness, and further prevents the substrate from warping by use of the stabilizing fixing structure.
Abstract translation: 公开了一种封装芯片和基板的方法，包括以下步骤：形成厚度范围为70-150μm的基板，该基板包括介电层，堆叠在电介质层上的电路金属层和高于 介电层10〜15μm; 在所述基板周围形成稳定结构以提供接收空间; 将芯片放置在接收空间上，并将芯片的引脚与焊盘接合; 并用填充材料填充芯片下方的接收空间，总厚度为300至850μm。 没有塑料成型工艺，本发明降低了成本和总厚度，并且通过使用稳定固定结构进一步防止了基板翘曲。
-
公开(公告)号：US09095085B2
公开(公告)日：2015-07-28
申请号：US13853325
申请日：2013-03-29
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
CPC classification number: H05K3/4647 , H05K3/4038 , H05K2203/025 , H05K2203/063 , Y10T29/49155
Abstract: Disclosed is a method of manufacturing a stacked multilayer structure, including the steps of forming a first circuit layer with bumps on a substrate, punching an aluminum plate to form recesses corresponding to the bumps, forming openings in a plastic film including a glass fiber layer corresponding to the bumps, pressing the aluminum plate, the plastic film and the substrate, removing the aluminum plate, polishing to level the resulting surface, forming a second circuit layer connected to the first circuit layer, and finally removing the substrate to form the stacked multilayer structure. Because the glass fiber layer in the plastic film is not exposed after polishing, the thickness of the dielectric layer is uniform and the reliability of the circuit layer is improved so as to increase the yield.
Abstract translation: 公开了一种制造堆叠多层结构的方法，包括以下步骤：在基板上形成具有凸块的第一电路层，冲压铝板以形成与凸块相对应的凹部，在包括玻璃纤维层的塑料膜中形成开口 对铝合金板，塑料薄膜和基板进行压制，去除铝板，进行抛光以使所得表面平坦化，形成连接到第一电路层的第二电路层，最后移除基板以形成叠层多层 结构体。 由于塑料膜中的玻璃纤维层在研磨后不露出，所以介电层的厚度均匀，电路层的可靠性得以提高，从而提高产率。
-
公开(公告)号：US08875390B2
公开(公告)日：2014-11-04
申请号：US13663274
申请日：2012-10-29
Applicant: Kinsus Interconnect Technology Corp.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC: H01K3/00
CPC classification number: H05K3/4682 , H05K1/0271 , H05K2201/09136 , H05K2201/2018 , H05K2203/0152 , H05K2203/0376 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/4916
Abstract: A method of manufacturing a laminate circuit board which includes the sequential steps of metalizing the substrate to form the base layer, forming the first circuit metal layer, forming at least one insulation layer and at least one second circuit metal layer interleaved, removing the substrate, forming the support frame and forming the solder resist is disclosed. The laminate circuit board has a thickness less than 150 μm. The support frame which does not overlap the first circuit metal layer is formed on the edge of the base layer by the pattern transfer process after the substrate is removed. The base layer formed of at least one metal layer is not completely removed. The support frame provides enhanced physical support for the entire laminate circuit board without influence on the electrical connection of the circuit in the second circuit metal layer, thereby solving the warping problem.
Abstract translation: 一种叠层电路板的制造方法，其特征在于，包括使所述基板金属化以形成所述基底层的顺序步骤，形成所述第一电路金属层，形成至少一个绝缘层和交替插入的至少一个第二电路金属层，去除所述基板， 公开了形成支撑框架并形成阻焊剂的方法。 层叠电路板的厚度小于150μm。 在去除衬底之后，通过图案转印工艺在基层的边缘上形成不与第一电路金属层重叠的支撑框架。 由至少一个金属层形成的基底层没有被完全去除。 支撑框架对整个层叠电路板提供增强的物理支撑，而不影响第二电路金属层中的电路的电连接，从而解决翘曲问题。
-
-
-
-
-
-
-
-
-
Search Results
14
records
(took 0.036 seconds)
