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1.发明申请公开(公告)号：US20190059153A1
公开(公告)日：2019-02-21
申请号：US15826692
申请日：2017-11-30
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Chin-Kuan Liu , Chao-Lung Wang , Shuo-Hsun Chang , Yu-Te Lu , Chin-Hsi Chang
CPC classification number: H05K1/0268 , H05K1/09 , H05K3/064 , H05K3/4644 , H05K3/4661 , H05K3/467 , H05K2201/0302 , H05K2203/072 , H05K2203/0723
Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a patterned metal-interface layer, a metallic delivery loading plate, an electrical connection layer, a conductive corrosion-barrier layer, a bottom dielectric layer, and a multi-layer circuit structure. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. The delivery loading plate and the patterned metal-interface layer expose the conductive corrosion-barrier layer. Therefore, before the multi-layer circuit board is packaged, an electrical testing can be applied to the multi-layer circuit board to check if it can be operated normally. Hence, costs for figuring out reasons of the unqualified electronic component can be reduced, and responsibilities for the unqualified electrical testing result of the electronic component can be clarified.
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2.发明授权公开(公告)号：US09301405B1
公开(公告)日：2016-03-29
申请号：US14604956
申请日：2015-01-26
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yi-Fan Kao , Jaen-Don Lan , Yu-Te Lu , Yung-Lin Chia , An-Ping Tseng
IPC: H01L21/4763 , H05K3/40 , H05K3/06 , H05K3/00 , H05K3/18 , H05K3/02 , H05K1/09 , H05K1/11 , H01L21/48
CPC classification number: H05K3/0035 , H01L21/4857 , H01L2924/01078 , H01L2924/014 , H05K1/115 , H05K3/007 , H05K3/064 , H05K3/421 , H05K3/429 , H05K2201/09536
Abstract: A method for manufacturing microthrough-hole includes electroplating a metal layer on a carrier plate, patterning the metal layer to form a first circuit having copper pads, covering the first circuit with a photoresist layer and not covering the copper window between two of the copper pads, etching the metal layer beneath the copper window and removing the photoresist layer, sequentially forming an insulation layer and a second circuit on the first circuit and the copper window, the second circuit layer having a stop pad corresponding to the copper window, removing the carrier plate, upward drilling through the insulation layer between the stop pad and the copper window to form a microthrough-hole beneath the stop pad, and forming a conductive layer in the microthrough-hole to form the microthrough-hole connecting the first and second circuits. The microthrough-hole and its occupied area is greatly reduced, thereby achieving high circuit density.
Abstract translation: 一种用于制造微通孔的方法包括在载体板上电镀金属层，图案化金属层以形成具有铜焊盘的第一电路，用光致抗蚀剂层覆盖第一电路，并且不覆盖两个铜焊盘之间的铜窗 蚀刻铜窗下方的金属层并除去光致抗蚀剂层，在第一电路和铜窗上依次形成绝缘层和第二电路，第二电路层具有对应于铜窗的停止焊盘，移除载体 通过止动垫和铜窗之间的绝缘层向上钻孔，以在止动垫下方形成微通孔，并在微通孔中形成导电层，形成连接第一和第二电路的微通孔。 微通孔及其占用面积大大降低，从而实现高电路密度。
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公开(公告)号：US08887386B2
公开(公告)日：2014-11-18
申请号：US13663333
申请日：2012-10-29
Applicant: Kinsus Interconnect Technology Corp.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC: H05K3/02
CPC classification number: H05K1/056 , H01L21/4857 , H01L21/486 , H01L23/13 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L2924/0002 , H05K1/0204 , H05K2201/029 , H05K2201/0323 , H05K2201/09054 , H05K2203/0323 , H05K2203/0384 , H05K2203/063 , Y10T29/49117 , Y10T29/49121 , Y10T29/49124 , Y10T29/49155 , Y10T29/49156 , H01L2924/00
Abstract: A method of manufacturing a chip support board structure which includes the steps of forming a metal substrate structure, forming a photo resist pattern, etching the metal substrate structure to form a paddle, removing the photo resist pattern, pressing an insulation layer against the paddle, polishing the insulation layer, forming a circuit layer and forming a solder resist is disclosed. The metal substrate structure is formed by sandwiching a block layer with two metal substrate layers, multilayer. The metal substrate structure is etched under control to an effective depth such that each paddle thus formed has the same shape and depth. Therefore, the method of the present invention can be widely applied to the general mass production processes to effectively solve the problems in the prior arts due to depth differences, such offset, position mismatch and peeling off in the chip support board.
Abstract translation: 一种制造芯片支撑板结构的方法，其包括以下步骤：形成金属基板结构，形成光致抗蚀剂图案，蚀刻金属基板结构以形成桨，去除光致抗蚀剂图案，将绝缘层压靠在桨上， 公开了抛光绝缘层，形成电路层和形成阻焊剂。 金属基板结构是通过将具有两个金属基底层的多层的阻挡层夹在中间而形成的。 在控制下将金属基底结构蚀刻到有效深度，使得如此形成的每个桨具有相同的形状和深度。 因此，本发明的方法可以广泛地应用于通常的批量生产过程，以有效地解决由于芯片支撑板中的深度差异，偏移，位置失配和剥离等现有技术的问题。
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公开(公告)号：US20140116755A1
公开(公告)日：2014-05-01
申请号：US13663250
申请日：2012-10-29
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC: H05K1/02
CPC classification number: H05K1/0271 , H05K3/4682 , H05K2201/09136 , H05K2201/2018
Abstract: A laminate circuit board structure which includes a first circuit metal layer, a first insulation layer, at least one second circuit metal layer, at least one second insulation layer and a support frame is disclosed. The total thickness of the laminate circuit board structure is less than 150 μm. The support frame provided at the outer edge of the co-plane surface formed by the first circuit metal layer and the first insulation layer does not cover the first circuit metal layer, and is formed of at least one metal material. The support frame provides physical support for the entire board structure without influence on the circuit connection so as to prevent the laminate circuit board structure from warping.
Abstract translation: 公开了一种层叠电路板结构，其包括第一电路金属层，第一绝缘层，至少一个第二电路金属层，至少一个第二绝缘层和支撑框架。 叠层电路板结构的总厚度小于150μm。 设置在由第一电路金属层和第一绝缘层形成的共面的外边缘处的支撑框架不覆盖第一电路金属层，并且由至少一种金属材料形成。 支撑框架为整个板结构提供物理支撑，而不影响电路连接，从而防止层压电路板结构翘曲。
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公开(公告)号：US20140115888A1
公开(公告)日：2014-05-01
申请号：US13663333
申请日：2012-10-29
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC: H05K3/06
CPC classification number: H05K1/056 , H01L21/4857 , H01L21/486 , H01L23/13 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L2924/0002 , H05K1/0204 , H05K2201/029 , H05K2201/0323 , H05K2201/09054 , H05K2203/0323 , H05K2203/0384 , H05K2203/063 , Y10T29/49117 , Y10T29/49121 , Y10T29/49124 , Y10T29/49155 , Y10T29/49156 , H01L2924/00
Abstract: A method of manufacturing a chip support board structure which includes the steps of forming a metal substrate structure, forming a photo resist pattern, etching the metal substrate structure to form a paddle, removing the photo resist pattern, pressing an insulation layer against the paddle, polishing the insulation layer, forming a circuit layer and forming a solder resist is disclosed. The metal substrate structure is formed by sandwiching a block layer with two metal substrate layers, multilayer. The metal substrate structure is etched under control to an effective depth such that each paddle thus formed has the same shape and depth. Therefore, the method of the present invention can be widely applied to the general mass production processes to effectively solve the problems in the prior arts due to depth differences, such offset, position mismatch and peeling off in the chip support board.
Abstract translation: 一种制造芯片支撑板结构的方法，其包括以下步骤：形成金属基板结构，形成光致抗蚀剂图案，蚀刻金属基板结构以形成桨，去除光致抗蚀剂图案，将绝缘层压靠在桨上， 公开了抛光绝缘层，形成电路层和形成阻焊剂。 金属基板结构是通过将具有两个金属基底层的多层的阻挡层夹在中间而形成的。 在控制下将金属基底结构蚀刻到有效深度，使得如此形成的每个桨具有相同的形状和深度。 因此，本发明的方法可以广泛地应用于通常的批量生产过程，以有效地解决由于芯片支撑板中的深度差异，偏移，位置失配和剥离等现有技术的问题。
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Patent Agency Ranking
公开(公告)号：US10548214B2
公开(公告)日：2020-01-28
申请号：US15826694
申请日：2017-11-30
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Chin-Kuan Liu , Chao-Lung Wang , Shuo-Hsun Chang , Yu-Te Lu , Chin-Hsi Chang
Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a metallic delivery loading plate, a bottom-layer circuit structure, a conductive corrosion-barrier layer, and a multi-layer circuit structure. The bottom-layer circuit structure is overlapping on the delivery loading plate. The conductive corrosion-barrier layer is disposed on the bottom dielectric layer. The multi-layer circuit structure is overlapping on the bottom-layer circuit structure. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the inner-layer circuit of the multi-layer circuit structure and the bottom-layer circuit of the bottom-layer circuit structure. The delivery loading plate and the bottom dielectric layer of the bottom-layer circuit structure expose the conductive corrosion-barrier layer.
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公开(公告)号：US10455694B2
公开(公告)日：2019-10-22
申请号：US16408431
申请日：2019-05-09
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Chin-Kuan Liu , Chao-Lung Wang , Shuo-Hsun Chang , Yu-Te Lu , Chin-Hsi Chang
Abstract: A manufacturing method for a multi-layer circuit board is provided. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer, the delivery loading plate and the patterned metal interface layer expose the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board to check if the multi-layer circuit board can be operated normally or not.
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公开(公告)号：US09370110B2
公开(公告)日：2016-06-14
申请号：US14225682
申请日：2014-03-26
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yu-Te Lu
CPC classification number: H05K3/4611 , H05K3/0094 , H05K3/10 , H05K3/205 , H05K3/28 , H05K3/3452 , H05K3/421 , H05K3/4658 , H05K2201/0376 , H05K2203/06 , H05K2203/0723 , H05K2203/143
Abstract: A method of manufacturing a multilayer substrate structure includes the steps of pre-treatment, pressing and post-treatment. A carrier plate provided with a circuit pattern layer is pressed against a plastic sheet. An interlayer connection pad is formed by drilling and filling the lower surface of the plastic sheet. The carrier plate, the plastic sheet, another plastic sheet and another carrier plate with a circuit pattern layer are pressed together, and then drilled/filled to form a multilayer stacked structure such that the two circuit pattern layers are indirectly and electrically connected to the interlayer connection pad, respectively. Therefore, it is possible to overcome the problem due to alignment tolerance by using the interlayer connection pad wider than alignment tolerance, and stacking the circuit layers, each having much finer line and smaller pitch.
Abstract translation: 制造多层基板结构的方法包括预处理，压制和后处理的步骤。 设置有电路图案层的承载板被压靠在塑料片上。 通过钻孔和填充塑料片的下表面形成夹层连接垫。 将载板，塑料片，另一塑料片和具有电路图案层的另一载体板压在一起，然后钻孔/填充以形成多层堆叠结构，使得两个电路图案层间接地并电连接到中间层 连接垫。 因此，可以通过使用比对准公差宽的层间连接焊盘来克服由于对准公差引起的问题，并且堆叠各个具有更细的线和更小间距的电路层。
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9.发明申请公开(公告)号：US20150282333A1
公开(公告)日：2015-10-01
申请号：US14225682
申请日：2014-03-26
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yu-Te Lu
CPC classification number: H05K3/4611 , H05K3/0094 , H05K3/10 , H05K3/205 , H05K3/28 , H05K3/3452 , H05K3/421 , H05K3/4658 , H05K2201/0376 , H05K2203/06 , H05K2203/0723 , H05K2203/143
Abstract: A method of manufacturing a multilayer substrate structure includes the steps of pre-treatment, pressing and post-treatment. A carrier plate provided with a circuit pattern layer is pressed against a plastic sheet. An interlayer connection pad is formed by drilling and filling the lower surface of the plastic sheet. The carrier plate, the plastic sheet, another plastic sheet and another carrier plate with a circuit pattern layer are pressed together, and then drilled/filled to form a multilayer stacked structure such that the two circuit pattern layers are indirectly and electrically connected to the interlayer connection pad, respectively. Therefore, it is possible to overcome the problem due to alignment tolerance by using the interlayer connection pad wider than alignment tolerance, and stacking the circuit layers, each having much finer line and smaller pitch.
Abstract translation: 制造多层基板结构的方法包括预处理，压制和后处理的步骤。 设置有电路图案层的承载板被压靠在塑料片上。 通过钻孔和填充塑料片的下表面形成夹层连接垫。 将载板，塑料片，另一塑料片和具有电路图案层的另一载体板压在一起，然后钻孔/填充以形成多层堆叠结构，使得两个电路图案层间接地并电连接到中间层 连接垫。 因此，可以通过使用比对准公差宽的层间连接焊盘来克服由于对准公差引起的问题，并且堆叠各个具有更细的线和更小间距的电路层。
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公开(公告)号：US20140290983A1
公开(公告)日：2014-10-02
申请号：US13853303
申请日：2013-03-29
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
CPC classification number: H05K3/4647 , H05K1/0366 , H05K3/38
Abstract: Disclosed is a stacked multilayer structure, including a first circuit layer having bumps, a plastic film stacked on the first circuit layer to fill up the space among the bumps so as to form a co-plane, and a second circuit layer formed on the co-plane and connected to the first circuit layer. The plastic film includes a glass fiber layer which is embedded and not exposed. The adhesion between plastic film and the second circuit layer is greatly improved because the glass fiber layer of the plastic film filling up the space among the bumps is not deformed and exposed outwards. Therefore, the yield and reliability of the stacked multilayer structure is increased.
Abstract translation: 公开了一种堆叠的多层结构，包括具有凸起的第一电路层，堆叠在第一电路层上以填充凸块之间的空间以形成共面的塑料膜，以及形成在共面上的第二电路层 平面并连接到第一电路层。 该塑料膜包括嵌入并不暴露的玻璃纤维层。 由于填充凸块之间的空间的塑料膜的玻璃纤维层不会变形并向外露出，所以塑料膜与第二电路层之间的粘合性大大提高。 因此，层叠多层结构的成品率和可靠性提高。
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