公开(公告)号：JPH08163116A

公开(公告)日：1996-06-21

申请号：JP31645094

申请日：1994-12-20

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： JIYO SEIIKU ,  KIN HOSHIMICHI ,  TEI KIHAN ,  SOU GENTETSU ,  RI KUNFUKU

IPC: H04M7/08 ,  H04J3/00 ,  H04J3/06 ,  H04L7/08

Abstract: PURPOSE: To realize the frame synchronization device to demultiplex a time division multiplex signal in parallel from an STM-4C structure of a broad band overall information communication network in compliance with the ITU-T recommendations. CONSTITUTION: A serial parallel conversion circuit 10 and a byte arrangement circuit 30 detect a frame byte from high speed reception data at a transmission rate of 622 Mbps, align bytes based on a detected time and provides an output of frame data as 8-bit parallel data. A synchronizing signal pattern detection circuit 90 and a consecutive pattern confirmation circuit 100 detect frame bytes continuously based on a low speed clock obtained by applying 8 frequency division from an original clock signal at a frequency divider circuit 70 to seek a frame synchronizing signal. As a result, the power consumption is reduced and the amount of the hardware is decreased.

公开(公告)号：JPH08172350A

公开(公告)日：1996-07-02

申请号：JP31531294

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SAI SOUKUN ,  SOU GENTETSU ,  RI KUNFUKU ,  YU MASATANE ,  KIN GENSAN

IPC: H03K19/086 ,  H03F1/02 ,  H03F3/45 ,  H03K19/0175

Abstract: PURPOSE: To obtain a CMOS buffer circuit with small power consumption and excellent high frequency response characteristic by connecting two output pads with two load resistors and deciding an output voltage with a current flowing to them. CONSTITUTION: A high level (+4 V) signal is given to a 1st input terminal 9 and a low level (+3 V) signal is given to a 2nd input terminal 10, then a 1st PMOS transistor(TR) 11 and a 2nd NMOS TR 14 are conductive and a current of 10 mA flows through load resistors 17, 18 from a 1st output pad 15 to a 2nd output pad 16. Thus, a voltage of 1 V is produced between the load resistors 17, 18. Then the 1st output pad 15 keeps a high level (+4 V) and the 2nd output pad 16 keeps a low level (+3 V). Conversely a low level signal is given to the 1st input terminal 9 and a high level signal is given to the 2nd input terminal 10, then the 1st output pad 15 keeps a low level voltage and the 2nd output pad 16 keeps a high level voltage.