公开(公告)号：JPH08163116A

公开(公告)日：1996-06-21

申请号：JP31645094

申请日：1994-12-20

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： JIYO SEIIKU ,  KIN HOSHIMICHI ,  TEI KIHAN ,  SOU GENTETSU ,  RI KUNFUKU

IPC: H04M7/08 ,  H04J3/00 ,  H04J3/06 ,  H04L7/08

Abstract: PURPOSE: To realize the frame synchronization device to demultiplex a time division multiplex signal in parallel from an STM-4C structure of a broad band overall information communication network in compliance with the ITU-T recommendations. CONSTITUTION: A serial parallel conversion circuit 10 and a byte arrangement circuit 30 detect a frame byte from high speed reception data at a transmission rate of 622 Mbps, align bytes based on a detected time and provides an output of frame data as 8-bit parallel data. A synchronizing signal pattern detection circuit 90 and a consecutive pattern confirmation circuit 100 detect frame bytes continuously based on a low speed clock obtained by applying 8 frequency division from an original clock signal at a frequency divider circuit 70 to seek a frame synchronizing signal. As a result, the power consumption is reduced and the amount of the hardware is decreased.

公开(公告)号：JPH07202705A

公开(公告)日：1995-08-04

申请号：JP29988094

申请日：1994-12-02

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SOU GENTETSU ,  GO SHIYOUJIYUN ,  RI SHIYOURETSU ,  SAI KAIKIYOKU ,  BAN SUTSUPU SON

IPC: G05F1/10 ,  H03M1/36 ,  H03M1/74

Abstract: PURPOSE: To provide an accurate capacitor type voltage divider circuit having reduced power consumption by utilizing capacitor system instead of an existing resistor system. CONSTITUTION: Plural switching sections 311 to 313 are driver in accordance with predetermined 1st and 2nd clock signals 301, 305 and provide three reference voltage levels VR, VM, VSS to respective voltage divider capacitors 323, 324. A voltage divider section divides the reference voltage levels VR, VM, VSS to required values. In this case, output voltage (Vri) is expressed by Vri=(VR×Ci2+VSS×Ci1)/(Ci1+Ci2), where Ci1, Ci2 are voltage dividing capacitance values.

公开(公告)号：JPH07202651A

公开(公告)日：1995-08-04

申请号：JP29977094

申请日：1994-12-02

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SOU GENTETSU ,  GO SHIYOUJIYUN ,  RI SHIYOURETSU ,  SAI KAIKIYOKU ,  BAN SUTSUPU SON

IPC: G11C11/409 ,  G11C7/06 ,  H03F3/45 ,  H03K3/356 ,  H03K5/08 ,  H03K5/24 ,  H03M1/34

Abstract: PURPOSE: To suppress the consumption of currents by instantaneously changing the signal levels of two output terminals for outputting current signals when the logical level of a latch signal is changed, and in steady operation, outputting no current signal. CONSTITUTION: At the time of latch operation holding a latch signal LB at a high logical level, current signals I51, I52 converted by a signal conversion part 50 are supplied to transistors(TRs) Q81, Q82 in an amplification/ determination part 80 through TRs Q64, Q62 in a switching part 60. When the signal LB is at a low logical level and there is no latch operation, the voltage levels of output terminals OUT1, OUT2 are held at a high logical level by a high level holding part 70 to set up an output holding state. Only during a steady operation, a circuit current is turned to '0' by the output signal feedback of an output feedback part 90. Consequently only when the logical level of the signal LB is changed, the signal levels of the terminals OUT1, OUT2, are instantaneously changed and allowed to flow out from the comparator. Since there is no current outflow during stready operation, current consumption can be suppressed.

公开(公告)号：JPH08172350A

公开(公告)日：1996-07-02

申请号：JP31531294

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SAI SOUKUN ,  SOU GENTETSU ,  RI KUNFUKU ,  YU MASATANE ,  KIN GENSAN

IPC: H03K19/086 ,  H03F1/02 ,  H03F3/45 ,  H03K19/0175

Abstract: PURPOSE: To obtain a CMOS buffer circuit with small power consumption and excellent high frequency response characteristic by connecting two output pads with two load resistors and deciding an output voltage with a current flowing to them. CONSTITUTION: A high level (+4 V) signal is given to a 1st input terminal 9 and a low level (+3 V) signal is given to a 2nd input terminal 10, then a 1st PMOS transistor(TR) 11 and a 2nd NMOS TR 14 are conductive and a current of 10 mA flows through load resistors 17, 18 from a 1st output pad 15 to a 2nd output pad 16. Thus, a voltage of 1 V is produced between the load resistors 17, 18. Then the 1st output pad 15 keeps a high level (+4 V) and the 2nd output pad 16 keeps a low level (+3 V). Conversely a low level signal is given to the 1st input terminal 9 and a high level signal is given to the 2nd input terminal 10, then the 1st output pad 15 keeps a low level voltage and the 2nd output pad 16 keeps a high level voltage.

公开(公告)号：JPH0750575A

公开(公告)日：1995-02-21

申请号：JP34420192

申请日：1992-12-24

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SHIN KISEN ,  SOU GENTETSU ,  KIN HOSHIMICHI

IPC: H03K17/04 ,  H03K17/66 ,  H03K19/013 ,  H03K19/018 ,  H03K19/086

Abstract: PURPOSE: To obtain a quicker switching characteristic, without adding elements nor changing a current by considerably reducing the impedance which drives a capacitor. CONSTITUTION: An output part 130 includes an emitter follower transistor TR 212, which is connected between a first power terminal VCC and an output node 213 and is turned on by the voltage level of a collector node 111 of a TR 102, a pull-down TR 214 which is connected between the output node 213 and a second power terminal VEE, a TR 216 which is turned on by the voltage level of a collector node 110 of a TR 101 connected between the first power terminal VCC and a node 211, and a resistance 215 and a capacitor 217 which are connected in parallel between the node 211 and a node 218, which generates a voltage for drive of the pull-down TR 214.

公开(公告)号：JPH07212141A

公开(公告)日：1995-08-11

申请号：JP33174892

申请日：1992-12-11

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SOU GENTETSU

IPC: H03F1/56 ,  H03F3/343 ,  H03F3/46

Abstract: PURPOSE: To reduce the error of offset currents, and to increase an output voltage swithcing level by providing a current mirror circuit which supplies bias current to a transistor for buffering an input signal and a current mirror circuit for offsetting base currents. CONSTITUTION: When the magnitude of the collector current of a main transistor Tr21 is defined as Ic, base current 213 is represented by Ic/β (above β is the current gain of Tr), and emitter current 211 by Ic(β+1)/β. Current 211 is the collector current of a Tr22, and the magnitude of base current 212 is equal to Ic(β+1)/β . On the other hand, Tr22 and Tr23 are of the same size to form a current offsetting circuit, and the base currents of the Tr23 and the Tr22 are the same. The magnitude of emitter current 214 of a Tr24 which supplies the base currents of the Tr22 and 23 is 2.Ic(β+1)/β , and collector current 215 is 2.Tc/β. At this time, the ratio of surface area of the Tr 25 and 26 of a mirror circuit 29b is 2:1, and the ratio of input and output currents 215:216 is 2:1, and output current 216=Ic/β is applied to the base of the T21, and offset to be the same magnitude of the current 213.

公开(公告)号：JPH05342871A

公开(公告)日：1993-12-24

申请号：JP34420092

申请日：1992-12-24

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： GO SHIYOUJIYUN ,  KEN SUIKI ,  SOU GENTETSU ,  KIN OUCHIYUU ,  KIN DAIYOU

IPC: G11C11/409 ,  G11C11/40

Abstract: PURPOSE: To reduce the delay time of a sensing operation by switch transistor for permitting assigning a load transistor pair of a sense amplifier group to each sense amplifier and providing a switch transistor which separates the output node of the amplifier and a main amplifier. CONSTITUTION: The output signal waveform of a column decoder 120 is delayed for a time required for permitting a signals of the output node pair 111 and 112 in a sense back-up circuit 100 to reach a prescribed reference level by a delay element 17 which is connected between an output node pairs 113 and 114 being different from plural sense amplifiers so as to be added to the gates of transistors Tr 15 and 16. Thus, Trs 15 and 16 are made to be in a conductive state, metallic line parasite capacitances 10 and 20 are connected to the nodes 111 and 112, the voltage of the node 111 is rapidly lowered and the voltage of the node 112 is lowered relatively gradually. Then, the main amplifier 30 is operated when control signals CNTL1 and CNTL2 are inputted and the voltages of the nodes 113 and 114 are instantaneously separated.