公开(公告)号：JPH07202873A

公开(公告)日：1995-08-04

申请号：JP29122694

申请日：1994-11-25

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SAI SOUKUN ,  BOKU FUMIHARU ,  KAKU MEISHIN ,  SAI KAIKIYOKU

IPC: H03K27/00 ,  H03L7/087 ,  H03L7/089 ,  H03L7/14 ,  H04J3/06 ,  H04L7/00 ,  H04L7/033

Abstract: PURPOSE: To supply a stabilized cock even when the input of a data signal or power supply is not normal. CONSTITUTION: When power is normally supplied and data signal is normally inputted, a loop selection switch 30 outputs a state '1' and a 1st loop circuit is selected. At this time, the phase of the data signal is compared with a clock outputted from a voltage controlled oscillator(VCO) 4 and a synchronizing clock is generated. In the case of restoring the system after a short-circuiting of a transmission line, the transmission interruption of a data signal or the interruption of power supply, a data signal monitoring part 40 or a power supply monitoring part 50 outputs a state '1', so that the switch 30 selects a 2nd loop. Then the phase of a reference clock built in the system itself is compared with that of a clock outputted from a VCO 28 to generate a synchronizing clock.

公开(公告)号：JPH0193159A

公开(公告)日：1989-04-12

申请号：JP17827188

申请日：1988-07-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIN KOUSHIYU ,  SAI SOUKUN ,  GU YOUSHIYO ,  KIN JIYOKAN ,  RI SHINKOU

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

Abstract: PURPOSE: To ensure high speed and high integration characteristics by simultaneously fabricating a high speed bipolar transistor with self alignment of polycrystalline Si and a high integration CMOS device using one wafer. CONSTITUTION: The surface of a P type substrate (Si wafer) 1 is ion implanted with As using a buried layer mask to form N type buried layers 2, 3 and an N type epitaxial layer 4 is grown over the entire surface of the substrate. The layer 4 is ion implanted with B using an oxide film mask to form a P type well 5, and after the oxide film is formed, a Si3 N4 film is deposited. The inside of the layer 4 is ion implanted with B to form a P type junction isolation layer 6, and an oxide film is grown, and further a device isolation region 7 and an insulating layer 8 are formed. B, P are implanted using a mask to form a P type base region 9 and an N type collector region 10, and As is implanted to form an N type polycrystal Si layer 11 on which an oxide film 12 is deposited. Then, gates 13, 14, an emitter 15, and a collector 16 are simultaneously formed. Further, sources/drains 17, 18 and 19, 20 are formed.

公开(公告)号：JPH0738066A

公开(公告)日：1995-02-07

申请号：JP33820391

申请日：1991-12-20

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： RI KIKOU ,  SAI SOUKUN ,  YO JUNICHI ,  KIN CHINSHIYOU ,  RI SHINKOU

IPC: H01L27/10 ,  H01L21/337 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/808

Abstract: PURPOSE: To provide a product having a vertical structure for realizing a highly integrated structure with reduced area of basic cells by arranging switching junction field transistors and storing capacitors to form the vertical structure. CONSTITUTION: Switching junction field transistors are formed on a semiconductor substrate 1, and storing capacitors are stacked on the junction field transistors to arrange these transistors and capacitors in the form of a vertical structure. The transistor has a gate region at a trench sidewall bottom formed by etching the substrate 1, word line 10a insulated from other element word lines through an insulation film 13 and active region 16 on the substrate 1. The storing capacitor has a storage node on a drain junction region, dielectric film 18 on the top of this node, and polysilicon film 19 for a plate electrode which is insulated from the storage node through an oxide film.

公开(公告)号：JPS6273667A

公开(公告)日：1987-04-04

申请号：JP14797986

申请日：1986-06-24

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SAI SOUKUN ,  RI SHINKOU

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/285 ,  H01L21/308 ,  H01L21/331 ,  H01L29/70 ,  H01L29/732

公开(公告)号：JPH08172350A

公开(公告)日：1996-07-02

申请号：JP31531294

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SAI SOUKUN ,  SOU GENTETSU ,  RI KUNFUKU ,  YU MASATANE ,  KIN GENSAN

IPC: H03K19/086 ,  H03F1/02 ,  H03F3/45 ,  H03K19/0175

Abstract: PURPOSE: To obtain a CMOS buffer circuit with small power consumption and excellent high frequency response characteristic by connecting two output pads with two load resistors and deciding an output voltage with a current flowing to them. CONSTITUTION: A high level (+4 V) signal is given to a 1st input terminal 9 and a low level (+3 V) signal is given to a 2nd input terminal 10, then a 1st PMOS transistor(TR) 11 and a 2nd NMOS TR 14 are conductive and a current of 10 mA flows through load resistors 17, 18 from a 1st output pad 15 to a 2nd output pad 16. Thus, a voltage of 1 V is produced between the load resistors 17, 18. Then the 1st output pad 15 keeps a high level (+4 V) and the 2nd output pad 16 keeps a low level (+3 V). Conversely a low level signal is given to the 1st input terminal 9 and a high level signal is given to the 2nd input terminal 10, then the 1st output pad 15 keeps a low level voltage and the 2nd output pad 16 keeps a high level voltage.

公开(公告)号：JPH05326854A

公开(公告)日：1993-12-10

申请号：JP27369991

申请日：1991-10-22

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SAI SOUKUN ,  GU YOUSHIYO ,  KIN KOUSHIYU ,  MINAMI MOTOMORI

IPC: H01L21/8249 ,  H01L27/06

Abstract: PURPOSE: To reduce the capacitive components of parts by reducing the inactive base region of a bipolar transistor and source-drain region of a CMOS transistor. CONSTITUTION: This method comprises the steps of depositing a crystal Si film 8, oxide film 9 and nitride film 10 to form emitters and collectors of bipolar elements and gates of CMOS elements, forming an oxide film 11 and second oxide film 12 at both side faces of a polycrystalline Si film 18, etching the exposed surface of an epitaxial layer 3, forming a third nitride film 13 on the side faces of a second nitride film, growing an oxide film 14 on the epitaxial layer 3, removing the nitride films 10, 12, 13 to expose an epitaxial layer 16, implanting impurities in this layer 16 to form p -type regions portions 17 for forming base regions of the bipolar elements and source and drain regions of PMOS elements, and forming n -type regions at portions 18 for forming source and drain regions of NMOS elements.