公开(公告)号：JP2000089054A

公开(公告)日：2000-03-31

申请号：JP29736998

申请日：1998-10-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： RI SANKAN ,  SHU KANSHU ,  KO NAN ,  SONG MIN-KYU

IPC: H01L31/00 ,  G02B6/122 ,  G02B6/13 ,  G02B6/136 ,  G02B6/30 ,  G02B6/36 ,  G02B6/42 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To minimize alignment error of transcription and to realize a manufacturing method of a substrate for a hybrid optical integrated circuit provided with an antireflection film which is optimized to a cross section of an optical waveguide. SOLUTION: The manufacturing method of a substrate for a hybrid optical integrated circuit has the first step in which a SOI slab 55 is formed by selatively etching a silicon layer of a SOI wafer, the second step in which silicon nitride films 57, 58 and an antietching film are formed on an upper part of the SOI wafer, the third step in which single crystal silicon of the slab is exposed by etching and a V-groove etched window 64 for aligning optical fiber and a mark 62 for aligning optical element are formed, the fourth step in which a SOI rib is formed by etching the exposed single crystal silicon layer, the fifth step in which the antietching film and the silicon nitride films 57, 58 are removed, the sixth step in which a cladding layer of the optical waveguide is formed on a surface of the SOI slab 55, the seventh step in which the V-groove for aligning the optical fiber is formed by anisotropically etching the silicon substrate exposed to the V-groove etched window 64 for aligning the optical fiber, and the eighth step in which the antietching film in a region adjacent to both end faces of the SOI slab 55 is removed to expose the silicon nitride film.

公开(公告)号：JP2000019363A

公开(公告)日：2000-01-21

申请号：JP30889598

申请日：1998-10-29

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KANG SEUNG-GOO ,  SONG MIN-KYU ,  RI KITAI

IPC: G02B6/02 ,  G02B6/42 ,  G02B7/00

Abstract: PROBLEM TO BE SOLVED: To make it possible to correct the deviation in alignment which occurs at the time of manufacturing a multichannel optical element module by providing the method with a step for assembling by utilizing laser welding and a step for forming at least one weld zone in the prescribed position of an optical fiber supporting base by utilizing the shrinkage effect of a welding section. SOLUTION: This method for correcting a laser corrects displacement by moving an optical fiber array 1 not only in horizontal (x), perpendicular (y) and axial (z) directions but in rotating (Rx, Ry, Rz) directions with respect to respective axes and utilizing the shrinkage effect of the welding section in order to correct the light alignment to all the directions. The optical fiber supporting base 20 includes erecting plates 21 which are erected on both sides apart a prescribed spacing in order to support an optical fiber ferrule in order to effectively apply such laser correction. These erecting plates 21 are formed to a thickness 21a as thin as about 300 to 400 micrometers and are easily shrunk by the irradiation with the laser beam, by which the regulation of the displacement is made possible.

公开(公告)号：DE4424549A1

公开(公告)日：1995-01-19

申请号：DE4424549

申请日：1994-07-12

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIM DONG-GOO ,  SONG MIN-KYU ,  PARK SEONG-SU ,  KANG SEUNG-GOO ,  YOON HYUNG-JIN ,  PARK HYUNG-MOO

IPC: H01L21/52 ,  H01L23/02 ,  H01L23/04 ,  H01L23/28 ,  H01L23/433 ,  H01L23/48 ,  H01L23/495 ,  H01L23/60 ,  H01L23/66 ,  H01L23/12 ,  H01L23/36 ,  H01L21/50

Abstract: A method of packaging a power semiconductor device is disclosed, comprising the steps of preparing a lead frame including a paddle for providing a semiconductor chip on a top surface thereof, tie bars for supporting said paddle, wherein said paddle being provided lower in horizontal surface than the leads; attaching a heat radiating plate on a bottom surface of the paddle by cladding; attaching a Kovar plate on the top surface of the paddle by soldering, said Kovar plate having similar heat expansion coefficient to that of the chip; providing the chip on the Kovar plate by soldering; wire-bonding terminals of said semiconductor chip to the corresponding leads of the lead frame, respectively; coating polyimide over the semiconductor chip by spin-coating; curing the polyimide coated thus; forming a metal cap above the said paddle by soldering, and injecting a molding material into a molder for enclosing the paddle and curing the molding material injected thus the method can be applied to produce a plastic package of a power semiconductor device at low cost. The metal cap is grounded through the tie bars as a source electrode to shield a noise.

公开(公告)号：GB2280062B

公开(公告)日：1997-04-09

申请号：GB9413867

申请日：1994-07-08

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIM DONG-GOO ,  SONG MIN-KYU ,  PARK SEONG-SU ,  KANG SEUNG-GOO ,  YOON HYUNG-JIN ,  PARK HYUNG MOO

IPC: H01L23/02 ,  H01L21/52 ,  H01L23/04 ,  H01L23/28 ,  H01L23/433 ,  H01L23/48 ,  H01L23/495 ,  H01L23/60 ,  H01L23/66 ,  H01L23/34

Abstract: A method of packaging a power semiconductor device is disclosed, comprising the steps of preparing a lead frame including a paddle for providing a semiconductor chip on a top surface thereof, tie bars for supporting said paddle, wherein said paddle being provided lower in horizontal surface than the leads; attaching a heat radiating plate on a bottom surface of the paddle by cladding; attaching a Kovar plate on the top surface of the paddle by soldering, said Kovar plate having similar heat expansion coefficient to that of the chip; providing the chip on the Kovar plate by soldering; wire-bonding terminals of said semiconductor chip to the corresponding leads of the lead frame, respectively; coating polyimide over the semiconductor chip by spin-coating; curing the polyimide coated thus; forming a metal cap above the said paddle by soldering, and injecting a molding material into a molder for enclosing the paddle and curing the molding material injected thus the method can be applied to produce a plastic package of a power semiconductor device at low cost. The metal cap is grounded through the tie bars as a source electrode to shield a noise.

公开(公告)号：GB2280062A

公开(公告)日：1995-01-18

申请号：GB9413867

申请日：1994-07-08

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIM DONG-GOO ,  SONG MIN-KYU ,  PARK SEONG-SU ,  KANG SEUNG-GOO ,  YOON HYUNG-JIN ,  PARK HYUNG MOO

IPC: H01L23/02 ,  H01L23/04 ,  H01L21/52 ,  H01L23/28 ,  H01L23/433 ,  H01L23/48 ,  H01L23/495 ,  H01L23/60 ,  H01L23/66 ,  H01L23/34

Abstract: A method of packaging a power semiconductor device is disclosed, comprising the steps of preparing a lead frame including a paddle (12) for providing a semiconductor chip (40) on a top surface thereof, and tie bars for supporting said paddle (12); wherein said paddle (12) is, provided lower in a horizontal surface than the leads (13, 14); attaching a heat radiating plate (20) on a bottom surface of the paddle (12) by cladding; attaching a Kovar plate (30) on the top surface of the paddle (12) by soldering, said Kovar plate (30) having similar heat expansion coefficient to that of the chip (40); providing the chip (40) on the Kovar plate (30) by soldering; wire-bonding terminals of said semiconductor chip (40) to the corresponding leads of the lead frame, respectively; coating polyimide over the semiconductor chip (40) by spin-coating; curing the polyimide coated thus; forming a metal cap above the said paddle (12) by soldering, and injecting a molding material into a molder for enclosing the paddle (12) and curing the molding material injected thus. The method can be applied to produce a plastic package of a power semiconductor device at low cost. The metal cap is grounded through the tie bars as a source electrode to shield against noise.

公开(公告)号：DE4424549C2

公开(公告)日：1996-10-17

申请号：DE4424549

申请日：1994-07-12

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIM DONG-GOO ,  SONG MIN-KYU ,  PARK SEONG-SU ,  KANG SEUNG-GOO ,  YOON HYUNG-JIN ,  PARK HYUNG-MOO

IPC: H01L21/52 ,  H01L23/02 ,  H01L23/04 ,  H01L23/28 ,  H01L23/433 ,  H01L23/48 ,  H01L23/495 ,  H01L23/60 ,  H01L23/66 ,  H01L23/12 ,  H01L23/36 ,  H01L21/50

Abstract: A method of packaging a power semiconductor device is disclosed, comprising the steps of preparing a lead frame including a paddle for providing a semiconductor chip on a top surface thereof, tie bars for supporting said paddle, wherein said paddle being provided lower in horizontal surface than the leads; attaching a heat radiating plate on a bottom surface of the paddle by cladding; attaching a Kovar plate on the top surface of the paddle by soldering, said Kovar plate having similar heat expansion coefficient to that of the chip; providing the chip on the Kovar plate by soldering; wire-bonding terminals of said semiconductor chip to the corresponding leads of the lead frame, respectively; coating polyimide over the semiconductor chip by spin-coating; curing the polyimide coated thus; forming a metal cap above the said paddle by soldering, and injecting a molding material into a molder for enclosing the paddle and curing the molding material injected thus the method can be applied to produce a plastic package of a power semiconductor device at low cost. The metal cap is grounded through the tie bars as a source electrode to shield a noise.