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    ADAPTABLE READOUT INTERFACE CIRCUIT FOR ION SENSORS
    1.
    发明专利
    ADAPTABLE READOUT INTERFACE CIRCUIT FOR ION SENSORS 未知

    公开(公告)号：MY173978A

    公开(公告)日：2020-03-02

    申请号：MYPI20090068

    申请日：2009-01-08

    Applicant: MIMOS BERHAD

    Inventor： NABIHAH RAZALI ,  ROZAIMAH BAHARIM ,  ROHANA MUSA ,  YUZMAN YUSOFF ,  MOHD SHAHIMAN SULAIMAN ,  HASMAYADI ABDUL MAJID ,  WEE LEONG SON ,  HANIF CHE LAH ,  ROHAYA ABDUL WAHAB ,  TAN KONG YEW ,  SHARIFAH SALEH ,  NAZALIZA OTHMAN

    Abstract: An adaptable readout interface circuit ( 1 0) comprising three operational amplifiers (11, 12, 13), a plurality of resistors (25, 26, 27), an adjustable gain resistor (15) and an offset voltage provider ( 16) is described. The first operational amplifier ( 11) is configured as an analog buffer wherein the output terminal provides feedback to its negative input terminal. An ion sensor (17) coupled to the positive terminal of the first operational amplifier. The second operational amplifier (12) is configured as an analog buffer wherein the output terminal provides feedback to its negative input terminal. A reference electrode (18) coupled to the positive terminal of the second operational amplifier. A gain resistor (15) is coupled to the negative terminal of the third operational amplifier to configure the third operational amplifier (13) as a gain amplifier. The output voltage of third operational amplifier provides an adjusted sensitivity and direct current level of ion sensor reading

    A COMPARISON SYSTEM FOR A HIGH RESOLUTION ADC AND METHOD THEREOF
    2.
    发明专利
    A COMPARISON SYSTEM FOR A HIGH RESOLUTION ADC AND METHOD THEREOF 未知

    公开(公告)号：MY187915A

    公开(公告)日：2021-10-28

    申请号：MYPI2017000183

    申请日：2017-02-06

    Applicant: MIMOS BERHAD

    Inventor： TAN KONG YEW

    IPC: H03M1/00 ,  H03K5/1252 ,  H03M1/10 ,  H03M1/12

    Abstract: The present invention introduces a comparison system in a successive- approximation-register (SAR) analog-to-digital converter (ADC) that improves the power consumption of conventional comparators. The comparator of the present invention specifically includes a dynamic latch (400), and an auto-triggered pre-amplifier (300) with an offset cancellation circuit and a two-stage differential operational amplifier (opamp). The dynamic latch (400) performs a coarse input comparison while the auto-triggered pre-amplifier (300) performs a finer input comparison, wherein the auto-triggered pre-amplifier (300) is triggered by a SAR logic (200) and a metastability detector (100) when the input difference signal resolution exceeds 10 bits.

    READOUT INTERFACE CIRCUIT FOR FEF SENSOR
    3.
    发明专利
    READOUT INTERFACE CIRCUIT FOR FEF SENSOR 未知

    公开(公告)号：MY173896A

    公开(公告)日：2020-02-26

    申请号：MYPI20090198

    申请日：2009-01-16

    Applicant: MIMOS BERHAD

    Inventor： NABIHAH RAZALI ,  ROHANA MUSA ,  YUZMAN YUSOFF ,  MOHD SHAHIMAN SULAIMAN ,  HASMAYADI ABDUL MAJID ,  WEE LEONG SON ,  HANIF CHE LAH ,  ROHAYA ABDUL WAHAB ,  TAN KONG YEW ,  SHARIFAH SALEH ,  NAZALIZA OTHMAN ,  ROZAIMAH BAHARIM

    Abstract: A readout interface circuit for a humidity sensor, particularly FEF sensor (10) is described. The readout interface circuit comprises a phase detector (20), a charge pump (30), a half wave rectifier (50) and two low pass filters (40, 42). The phase detector (20) is configured to produce output voltage proportional to the phase difference of signals from FEF sensor. The charge pump (30) is configured to control the current flow of phase detector to provide a linear output of phase detector. The first low pass filter (40) suppress noise level of charge pump output. The half wave rectifier (50) extracts the signal magnitude of sensor output. The second low pass filter (42) extract DC level of output of half wave rectifier. The output of first low pass filter (40) carries phase difference information of humidity and the output of second low pass filter (42) carries voltage output of humidity.

    AN ANALOGUE TO DIGITAL CONVERTER
    5.
    发明专利
    AN ANALOGUE TO DIGITAL CONVERTER 未知

    公开(公告)号：MY177180A

    公开(公告)日：2020-09-09

    申请号：MYPI2013002294

    申请日：2013-06-19

    Applicant: MIMOS BERHAD

    Inventor： HASMAYADI ABDUL MAJID ,  TAN KONG YEW

    Abstract: The present invention relates to a small area multi segment DAC that is used within a successive approximation analog to digital converter. The present invention comprising: a comparator (100) for comparing input signal with a reference signal; a successive approximation logic (200) that takes input from the comparator (100); and a digital to analogue converter block (300) including a plurality of capacitors that receives input from the successive approximation logic (200) block and generates reference signal that is applied to the comparator (100). The present invention not only combines the thermometer coded (3000) and binary coded segments (1000) but also a segment that has sub-radix 2 (radix

    AN ANALOG TO DIGITAL CONVERTER
    6.
    发明专利
    AN ANALOG TO DIGITAL CONVERTER 未知

    公开(公告)号：MY165440A

    公开(公告)日：2018-03-22

    申请号：MYPI2011700200

    申请日：2011-12-20

    Applicant: MIMOS BERHAD

    Inventor： NG MEI YEE ,  TAN KONG YEW

    IPC: H03M1/14 ,  H03M1/12 ,  H03M1/42 ,  H03M1/46

    Abstract: THE PRESENT INVENTION RELATES TO AN ANALOG TO DIGITAL CONVERTER (100). THE ANALOG TO DIGITAL CONVERTER (100) RESOLVES THE MOST SIGNIFICANT BITS BY USING ASYNCHRONOUS BINARY SEARCH METHOD AND THE REMAINING BITS BY USING CHARGE REDISTRIBUTION METHOD. THE ANALOG TO DIGITAL CONVERTER (100) COMPRISES OF A SAMPLE AND HOLD CIRCUIT (110), AN ANALOG COMPARATOR (120), A SUCCESSIVE APPROXIMATION REGISTER (130), A BINARY TREE OF COMPARATORS (140) AND A DIGITAL TO ANALOG CONVERTER OR DAC (150).

    BINARY WEIGHTED CAPACITOR ARRAY WITH SPLIT CAPACITOR LAYOUT
    7.
    发明专利
    BINARY WEIGHTED CAPACITOR ARRAY WITH SPLIT CAPACITOR LAYOUT 未知

    公开(公告)号：MY192587A

    公开(公告)日：2022-08-29

    申请号：MYPI2018001448

    申请日：2018-08-15

    Applicant: MIMOS BERHAD

    Inventor： TAN KONG YEW ,  ROHAYA BINTI ABDUL WAHAB

    IPC: H01L21/82 ,  H01L21/822 ,  H01L27/04

    Abstract: The present invention discloses a method of building a binary weighted split capacitor array (1) for minimizing routing induced parasitic mismatch. Specifically, the binary weighted split capacitor array is built with a plurality of unit capacitors with three- dimensional structures having a top plate comprising a plurality of stacked metal plates (M2, M3, M4, M5) and a bottom plate enclosing the top plate with side walls, a floor layer and a ceiling layer to minimize top plate parasitic capacitance to the substrate, and to achieve overall equal parasitic capacitance to the substrate. (Figure 15)

    A SYSTEM AND METHOD FOR CONVERTING AN ANALOGUE SIGNAL INPUT INTO A DIGITAL SIGNAL OUTPUT
    8.
    发明专利
    A SYSTEM AND METHOD FOR CONVERTING AN ANALOGUE SIGNAL INPUT INTO A DIGITAL SIGNAL OUTPUT 未知

    公开(公告)号：MY191343A

    公开(公告)日：2022-06-17

    申请号：MYPI2018002781

    申请日：2018-12-19

    Applicant: MIMOS BERHAD

    Inventor： TAN KONG YEW ,  SITI NOOR BT HARUN ,  FAUZIDAH BINTI KASSIM

    IPC: H03M1/06 ,  H03M1/40 ,  H03M1/46

    Abstract: The present invention relates to a system (1000) and method for converting an analogue signal input into a digital signal output. The system (1000) comprising a first circuit (100) configured to generate at least one digital output (DF) and at least one residual voltage (VREs) from at least one input voltage (V1N) and a second circuit (200) configured to generate at least one digital output (Os) from the residual voltage (VREs). The analogue-to-digital converter (1000) further comprises a third circuit (300) configured to correct the digital outputs (DF, Ds) in case of conversion error, combine the digital outputs (DF, D s), and generate a combined digital signal (De). The first circuit (100) further comprises a multiplier circuit (110) configured to apply gain to an analogue input signal, wherein the multiplier circuit (110) having a plurality of correlated level shifting capacitors (CcLs1, CcLs2, CcLs3) configured to perform level shifting sequentially.

    A SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER AND METHOD FOR CALIBRATING THEREOF
    9.
    发明专利
    A SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER AND METHOD FOR CALIBRATING THEREOF 未知

    公开(公告)号：MY184557A

    公开(公告)日：2021-04-02

    申请号：MYPI2014002905

    申请日：2014-10-10

    Applicant: MIMOS BERHAD

    Inventor： TAN KONG YEW

    Abstract: A Successive Approximation Analog to Digital Converter, SA-ADC (100) and a method for calibrating thereof has been disclosed. The SA-ADC (100) includes a capacitance measurement circuit (200) which performs frequency based capacitance measurement for calibrating the SA-ADC (100). The capacitance measurement circuit (200) is connected to a Digital to Analog Converter, DAC of SA-ADC (100) once only and thereafter the frequency based capacitance value of capacitors is repeatedly used in conversion cycles. Thus, the capacitance measurement circuit (200) improves conversion rate of conventional successive approximation analog to digital converters and eliminates the need for high accuracy DAC required in conventional SA-ADC.

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