公开(公告)号：US20250166898A1

公开(公告)日：2025-05-22

申请号：US18515291

申请日：2023-11-21

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chih-Chun HSIAO ,  Ji-Feng LIU

IPC: H01G4/008 ,  H01G4/12 ,  H01G4/38

Abstract: A method of manufacturing a capacitor includes forming a bottom electrode layer; forming an insulator on the bottom electrode layer; crystallizing the insulator; and forming a top electrode layer on the crystallized insulator. As such, the leakage problem due to thinner top electrode layer and smaller critical dimension of the capacitor can be reduced. In addition, possibility for the capacitors to collapse is reduced, and the electrical performance of the capacitor won't be affected by the collapse problem.

公开(公告)号：US20250133777A1

公开(公告)日：2025-04-24

申请号：US18491777

申请日：2023-10-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yen-Wei YEH ,  Ji-Feng LIU

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L29/161 ,  H01L29/45 ,  H01L29/49

Abstract: A semiconductor device includes a substrate, a channel layer, a source/drain region and a gate structure. The channel layer is located on the substrate, in which the channel layer includes silicon germanium. The source/drain region is adjacent to the channel layer. The gate structure is located on the channel layer, in which the gate structure includes a dielectric layer and a work function metal layer. The dielectric layer is located on the channel layer. The work function metal layer is located on the dielectric layer.

公开(公告)号：US20250006488A1

公开(公告)日：2025-01-02

申请号：US18341782

申请日：2023-06-27

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chao-Hsiu LI ,  Ji-Feng LIU

IPC: H01L21/02 ,  C23C16/455 ,  H01J37/32 ,  H01L23/16 ,  H01L23/528 ,  H01L23/532

Abstract: A deposition device includes a first chamber, a substrate support, a second chamber, a showerhead, a first reactant inlet, a second reactant, and a precursor inlet. The first chamber includes a diffusion zone and a reaction zone, and the diffusion zone is above the reaction zone. The substrate support is disposed in the reaction zone. The second chamber is disposed over the first chamber. The showerhead is disposed between the first chamber and the second chamber. The first reactant inlet communicates with the second chamber. The second reactant inlet communicates with the reaction zone of the first chamber. The precursor inlet communicates with the showerhead.

公开(公告)号：US20240379561A1

公开(公告)日：2024-11-14

申请号：US18144999

申请日：2023-05-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ji-Feng LIU

IPC: H01L23/532 ,  H01L21/768

Abstract: An interconnect structure includes a barrier layer, an oxide glue layer, and an ultra low-k dielectric layer. The oxide glue layer is located on the barrier layer. The ultra low-k dielectric layer is located on the oxide glue layer, wherein the oxide glue layer is located between the barrier layer and the ultra low-k dielectric layer, and the ultra low-k dielectric layer has porosity less than 40%.