公开(公告)号：GB2507124A

公开(公告)日：2014-04-23

申请号：GB201218933

申请日：2012-10-22

Applicant: ST MICROELECTRONICS GRENOBLE 2 ,  ST MICROELECTRONICS SRL

Inventor： MANGANO DANIELE ,  URZI IGNAZIO-ANTONINO ,  GRACIANNETTE NICOLAS

IPC: G06F13/14 ,  H04L47/30 ,  G06F15/78

Abstract: A first device sends data to a second device via a communication path across an interconnect. The second device sends feedback to the first device. The feedback may be the time taken for a request to reach the second device and the response to return to the first device. The feedback may be the amount of data stored in a buffer on the second device. This may be whether the amount of data exceeds a threshold. The first device adjusts the rate at which it outputs data to the second device based on the feedback. It may adjust the bandwidth allocated to the data or the frequency with which it transmits data. The first device may send a request for feedback via a different path to that on which the data is sent.

公开(公告)号：GB2521121A

公开(公告)日：2015-06-17

申请号：GB201319683

申请日：2013-11-07

Applicant: ST MICROELECTRONICS RES & DEV ,  ST MICROELECTRONICS GRENOBLE 2

Inventor： SARTA DAVIDE ,  URZI IGNAZIO-ANTONINO

IPC: G06F13/24

Abstract: A method comprises: capturing a set of interrupts; and outputting them serially onto an interconnect for routing to a destination. Only active interrupts may be output. Interrupts may be processed before output, and an interrupt status register may be updated each time an interrupt has been processed. While a first set of interrupts is being processed, a second set of interrupts may be being captured. The processing may comprise packetizing, and may comprise information about a type, destination, an interrupt level, or routing information. The interconnect may comprise a network on chip 208, 210, 212, 214. The packetized interrupt may be de-packetized or unpacked at the destination. Using an existing interconnect obviates the need for a complex arrangement of interrupt lines (Figure 3) which might otherwise occupy a significant silicon area.

公开(公告)号：GB2499374A

公开(公告)日：2013-08-21

申请号：GB201201530

申请日：2012-01-30

Applicant: ST MICROELECTRONICS GRENOBLE 2 ,  ST MICROELECTRONICS RES & DEV

Inventor： FERRIS ANDREW ,  URZI IGNAZIO-ANTONINO

IPC: G06F1/08

Abstract: Disclosed is a circuit arrangement with two clock sources and circuitry configured to supply a clock signal to an associated circuit. The circuitry is configured to change the clock signal from one frequency to another frequency such that no clock signal is supplied when changing the frequencies. The first source may be an oscillator, and the second may be a phase lock loop, which may setup to attain lock when the clock signal from the first clock source is being supplied. The circuit arrangement may have delay locked loop circuitry to provide a controllable delay. The associated circuit may have a plurality of taps, such that the selection of the taps determines the period for which the clock is not supplied and/or the time taken to change the supplied clock frequency. The circuit arrangement may be consist of a pair of dies, the first die having a processor and the second having a memory that stores boot data for the processor.