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公开(公告)号：JP2000347854A
公开(公告)日：2000-12-15
申请号：JP2000135053
申请日：2000-05-08
Applicant: ST MICROELECTRONICS SA
Inventor： COFLER ANDREW , WOJCIESZAK LAURENT , BOUVIER STEPHANE
Abstract: PROBLEM TO BE SOLVED: To provide a decoding device which is simple and good in power efficiency and supplies a decoding output to an execution device accurately according to an instruction mode of a computer. SOLUTION: The decoding device 20 is equipped with 1st and 2nd decoders 50 and 52, and 54 and 56 which are so connected as to receive bit arrays of 1st and 2nd specific lengths. The 1st and 2nd decoders operate in parallel so as to generate respective outputs. Switches MUX6 and MUX7 select one of the outputs according to an instruction mode of a processor. The instruction mode of this processor affects the length of the bit array which needs to actually be decoded.
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公开(公告)号：JP2000330788A
公开(公告)日：2000-11-30
申请号：JP2000135141
申请日：2000-05-08
Applicant: ST MICROELECTRONICS SA
Inventor： COFLER ANDREW , BOUVIER STEPHANE
Abstract: PROBLEM TO BE SOLVED: To decrease disadvantages in case of a failure in branching by previously holding a usable instruction to be executed by detecting a branch instruction and setting a branch shadow mode, and supplying the instruction continuously. SOLUTION: A program counter 80 is equipped with a takeout branch address unit 218 which holds a target address for branching. A general unit 21 transfers the target address to the takeout branch address unit 218 of a control unit 12 through a bus 23. Branch with a dummy guard is detected by a decoder 82 and the branch shadow mode is set. The branch shadow mode indicates that the setting is reset with a signal on a line 224 from the general unit 21 to the decoder and branching is determined. The branch shadow circuit constitution of the decoder 82 continues to supply instructions after the branch instruction with the dummy guard through a computer and the execution of all allowed following instructions is carried on.
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公开(公告)号：GB2362730A
公开(公告)日：2001-11-28
申请号：GB9930590
申请日：1999-12-23
Applicant: ST MICROELECTRONICS SA
Inventor： WOJCIESZAK LAURENT , SENAME ISABELLE , BOUVIER STEPHANE
Abstract: A system for executing a sequence of instructions and effecting changes in data held in one or more registers during execution of the instructions, the system including instruction fetch circuitry, decode circuitry to decode instructions and identify registers used in the execution of the instruction and dispatch circuitry to send instructions to one or more execution units after decoding. The system also includes emulator circuitry for debug operations which is arranged to watch data values in one or more selected registers modified during execution of the instructions. The circuitry further comprises a register watch store, for identifying registers to be watched, comparator circuitry, for comparing registers identified by the decode circuitry to registers identified by the register watch store and for recording a signal whenever these match and instruction insertion circuitry responsive to those signals to insert a store instruction to store in a location accessible by the emulation circuitry the data value in a data register identified by a hit signal after execution of the instruction using the data register into the instruction queue for an execution unit.
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公开(公告)号：GB2362730B
公开(公告)日：2004-02-11
申请号：GB9930590
申请日：1999-12-23
Applicant: ST MICROELECTRONICS SA
Inventor： WOJCIESZAK LAURENT , SENAME ISABELLE , BOUVIER STEPHANE
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