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    DEVICE AND METHOD FOR DECODING
    1.
    发明专利
    DEVICE AND METHOD FOR DECODING 失效

    公开(公告)号：JP2000347854A

    公开(公告)日：2000-12-15

    申请号：JP2000135053

    申请日：2000-05-08

    Applicant: ST MICROELECTRONICS SA

    Inventor： COFLER ANDREW ,  WOJCIESZAK LAURENT ,  BOUVIER STEPHANE

    IPC: G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38

    Abstract: PROBLEM TO BE SOLVED: To provide a decoding device which is simple and good in power efficiency and supplies a decoding output to an execution device accurately according to an instruction mode of a computer. SOLUTION: The decoding device 20 is equipped with 1st and 2nd decoders 50 and 52, and 54 and 56 which are so connected as to receive bit arrays of 1st and 2nd specific lengths. The 1st and 2nd decoders operate in parallel so as to generate respective outputs. Switches MUX6 and MUX7 select one of the outputs according to an instruction mode of a processor. The instruction mode of this processor affects the length of the bit array which needs to actually be decoded.

    COMPUTER SYSTEM EXECUTING INSTRUCTION LOOP AND INSTRUCTION LOOP EXECUTING METHOD
    2.
    发明专利
    COMPUTER SYSTEM EXECUTING INSTRUCTION LOOP AND INSTRUCTION LOOP EXECUTING METHOD 失效

    公开(公告)号：JP2000330787A

    公开(公告)日：2000-11-30

    申请号：JP2000135045

    申请日：2000-05-08

    Applicant: ST MICROELECTRONICS SA

    Inventor： WOJCIESZAK LAURENT ,  COFLER ANDREW

    IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38

    Abstract: PROBLEM TO BE SOLVED: To prevent electric power and a load from being applied on a memory access bus by locking a prefetch buffer for further access to a program memory when all loop instructions are present in the prefetch buffer. SOLUTION: A matching part 20 inspects a loop start address by a compactor 77 as to the address of a matching program counter 36. When the same loop start address match is stored in a special buffer 75, this means that a loop is completely included in the prefetch buffer 22. In this case, a lock signal is sent to the prefetch buffer 22. All loop instructions are held in the prefetch buffer 22 with a frequency where the loop instructions need to be executed. Therefore, the lock signal eliminates the need to take the loop instructions out of a program memory repeatedly until the loop is repeated with the prescribed frequency.

    Instruction execution using guard or prediction indicators
    4.
    发明专利
    Instruction execution using guard or prediction indicators 未知

    公开(公告)号：GB2362968A

    公开(公告)日：2001-12-05

    申请号：GB9930589

    申请日：1999-12-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： COFLER ANDREW ,  SENAME ISABELLE ,  BERNARD BRUNO ,  WOJCIESZAK LAURENT ,  DEHAMEL ARNAUD

    IPC: G06F9/38 ,  G06F11/36 ,  G06F11/07

    Abstract: A system for executing instructions having assigned guard or prediction indicators, the system comprising instruction supply circuitry, at least one pipelined execution unit for receiving instructions from the supply circuitry together with a guard or prediction indicator selected from a set of guard or prediction indicators. The execution unit includes a master guard value store containing master values for the guard indicators and circuitry for resolving the guard or prediction value of the guard or prediction indicator in the instruction pipeline and providing a signal to indicate if the pipeline is committed to executing the instruction. The system includes an emulator which has watch circuitry for watching selected instructions in the execution pipeline and synchronising circuitry for correlating resolution of the guard or prediction indicator of each selected instruction with a program count for that instruction.

    5.
    发明专利
    未知

    公开(公告)号：DE69934394D1

    公开(公告)日：2007-01-25

    申请号：DE69934394

    申请日：1999-05-03

    Applicant: ST MICROELECTRONICS SA

    Inventor： WOJCIESZAK LAURENT ,  COFLER ANDREW

    IPC: G06F9/38 ,  G06F9/30 ,  G06F9/318

    Abstract: An instruction prefetch buffer is described which has a powersave mechanism. A set of output devices of an instruction supply mechanism each have a stop switch which either pass on a changed bit sequence or the previously supplied bit sequence. If the previously supplied bit sequence is supplied, no power is utilised in that machine cycle.

    Using store instructions to watch registers
    9.
    发明专利
    Using store instructions to watch registers 未知

    公开(公告)号：GB2362730A

    公开(公告)日：2001-11-28

    申请号：GB9930590

    申请日：1999-12-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： WOJCIESZAK LAURENT ,  SENAME ISABELLE ,  BOUVIER STEPHANE

    IPC: G06F11/36 ,  G06F11/07

    Abstract: A system for executing a sequence of instructions and effecting changes in data held in one or more registers during execution of the instructions, the system including instruction fetch circuitry, decode circuitry to decode instructions and identify registers used in the execution of the instruction and dispatch circuitry to send instructions to one or more execution units after decoding. The system also includes emulator circuitry for debug operations which is arranged to watch data values in one or more selected registers modified during execution of the instructions. The circuitry further comprises a register watch store, for identifying registers to be watched, comparator circuitry, for comparing registers identified by the decode circuitry to registers identified by the register watch store and for recording a signal whenever these match and instruction insertion circuitry responsive to those signals to insert a store instruction to store in a location accessible by the emulation circuitry the data value in a data register identified by a hit signal after execution of the instruction using the data register into the instruction queue for an execution unit.

    10.
    发明专利
    未知

    公开(公告)号：DE69935066D1

    公开(公告)日：2007-03-22

    申请号：DE69935066

    申请日：1999-05-03

    Applicant: ST MICROELECTRONICS SA

    Inventor： WOJCIESZAK LAURENT ,  COFLER ANDREW

    IPC: G06F9/38 ,  G06F9/30 ,  G06F9/318

    Abstract: A prefetch buffer is described which supports a computer system having a plurality of different instruction modes. The number of storage locations which are read out of the prefetch buffer during each machine cycle is controlled in dependence on the instruction mode. Thus the prefetch buffer allows a number of different instruction modes to be supported and hides memory access latency.

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