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    LOW NOISE VERTICAL BIPOLAR TRANSISTOR AND FABRICATION THEREOF
    1.
    发明专利
    LOW NOISE VERTICAL BIPOLAR TRANSISTOR AND FABRICATION THEREOF 失效

    公开(公告)号：JP2000031155A

    公开(公告)日：2000-01-28

    申请号：JP15604999

    申请日：1999-06-03

    Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

    Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  DUTARTRE DIDIER ,  MONROY AUGUSTIN ,  LAURENS MICHEL ,  GUETTE FRANCOIS

    IPC: H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/737

    Abstract: PROBLEM TO BE SOLVED: To reduce low frequency noise while sustaining accurate current amplification factor by obtaining an emitter region of single crystal silicon touching the upper layer of a stack, e.g. silicon of an upper encapsulation layer of the stack, directly on a window. SOLUTION: On a silicon substrate 1, a buried extrinsic collector layer 2 doped with n+ by implanting arsenic and two buried layers 3 similarly doped with p+ are formed and a thick n-type single crystal silicon layer 4 is grown epitaxially. Subsequently, an amorphous silicon layer 17 is deposited on a semiconductor block thus formed and etched above an oxide layer 6 to form a window 170 which is then subjected to desorption. Thereafter, a stack 8 is formed, a silicon dioxide layer 9 and a silicon nitride layer 10 are deposited thereon and then the layers 9, 10 are removed from a desired zone to obtain an emitter, i.e., an emitter window 800.

    3.
    发明专利
    未知

    公开(公告)号：DE69800530T2

    公开(公告)日：2001-06-13

    申请号：DE69800530

    申请日：1998-03-10

    Applicant: ST MICROELECTRONICS SA

    Inventor： DO TIEN-DUNG ,  LISART MATHIEU PIERRE GABRIEL ,  GUETTE FRANCOIS

    IPC: H02M3/07

    Abstract: The circuit comprises stages connected in series to produce by transfer of loads between stages an output voltage derived from a feed voltage. The circuit comprises devices (REG,CC) for reducing or increasing the number of stages connected, in terms of the value of the voltage produced, so that the number of stages connected is adapted to the number of stages necessary in order to attain a given output voltage value, taking into account the value of the feed voltage. Commutation devices connect selectively at least one outlet of a stage (Cn-1) to and inlet of another stage or to a circuit outlet (S). A regulating circuit comprises comparison devices to compare the value of the output voltage produced (Vout) with an incrementation threshold with one of diminution. Devices are also provided for comparing the value of the voltage produced with a regulation threshold included between the thresholds of incrementation and of diminution in order to produce a first command signal (HIGH) representing the result of this comparison.

    5.
    发明专利
    未知

    公开(公告)号：DE69800530D1

    公开(公告)日：2001-03-29

    申请号：DE69800530

    申请日：1998-03-10

    Applicant: ST MICROELECTRONICS SA

    Inventor： DO TIEN-DUNG ,  LISART MATHIEU PIERRE GABRIEL ,  GUETTE FRANCOIS

    IPC: H02M3/07

    Abstract: The circuit comprises stages connected in series to produce by transfer of loads between stages an output voltage derived from a feed voltage. The circuit comprises devices (REG,CC) for reducing or increasing the number of stages connected, in terms of the value of the voltage produced, so that the number of stages connected is adapted to the number of stages necessary in order to attain a given output voltage value, taking into account the value of the feed voltage. Commutation devices connect selectively at least one outlet of a stage (Cn-1) to and inlet of another stage or to a circuit outlet (S). A regulating circuit comprises comparison devices to compare the value of the output voltage produced (Vout) with an incrementation threshold with one of diminution. Devices are also provided for comparing the value of the voltage produced with a regulation threshold included between the thresholds of incrementation and of diminution in order to produce a first command signal (HIGH) representing the result of this comparison.

    6.
    发明专利
    未知

    公开(公告)号：FR2779572A1

    公开(公告)日：1999-12-10

    申请号：FR9807059

    申请日：1998-06-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  DUTARTRE DIDIER ,  MONROY AUGUSTIN ,  LAURENS MICHEL ,  GUETTE FRANCOIS

    IPC: H01L21/331 ,  H01L29/08 ,  H01L29/737 ,  H01L29/73 ,  H01L29/732

    Abstract: A vertical bipolar transistor production process comprises epitaxy of a single crystal silicon emitter region in direct contact with the upper layer of a silicon germanium heterojunction base. Production of a vertical bipolar transistor comprises (a) forming an intrinsic collector (4) on an extrinsic collector layer buried in a semiconductor substrate (1); (b) forming a lateral insulation region (5) around the upper part of the intrinsic collector and an offset extrinsic collector well (60); (c) forming an silicon germanium heterojunction base above the intrinsic collector (4) and the lateral insulation region (5) by non-selective epitaxy of a multilayer (8) including a silicon germanium layer; and (e) forming an in-situ doped emitter by epitaxy on a window of the surface of the multilayer located above the intrinsic collector to obtain, above the window, a single crystal silicon emitter region in direct contact with the upper layer of the multilayer (8). An Independent claim is also included for a vertical bipolar transistor produced by the above process.

    7.
    发明专利
    未知

    公开(公告)号：FR2779572B1

    公开(公告)日：2003-10-17

    申请号：FR9807059

    申请日：1998-06-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  DUTARTRE DIDIER ,  MONROY AUGUSTIN ,  LAURENS MICHEL ,  GUETTE FRANCOIS

    IPC: H01L21/331 ,  H01L29/08 ,  H01L29/737 ,  H01L29/73 ,  H01L29/732

    Abstract: A vertical bipolar transistor production process comprises epitaxy of a single crystal silicon emitter region in direct contact with the upper layer of a silicon germanium heterojunction base. Production of a vertical bipolar transistor comprises (a) forming an intrinsic collector (4) on an extrinsic collector layer buried in a semiconductor substrate (1); (b) forming a lateral insulation region (5) around the upper part of the intrinsic collector and an offset extrinsic collector well (60); (c) forming an silicon germanium heterojunction base above the intrinsic collector (4) and the lateral insulation region (5) by non-selective epitaxy of a multilayer (8) including a silicon germanium layer; and (e) forming an in-situ doped emitter by epitaxy on a window of the surface of the multilayer located above the intrinsic collector to obtain, above the window, a single crystal silicon emitter region in direct contact with the upper layer of the multilayer (8). An Independent claim is also included for a vertical bipolar transistor produced by the above process.

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