公开(公告)号：JP2000164738A

公开(公告)日：2000-06-16

申请号：JP33768899

申请日：1999-11-29

Applicant: ST MICROELECTRONICS SA

Inventor： LAURENS MICHEL

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

Abstract: PROBLEM TO BE SOLVED: To reduce manufacturing step numbers and improve quality by etching a base Si outside a useful region, while leaving specified position on a thin oxide, forming collector contact regions at the same time as the drain injection of n-channel MOS transistors, and injecting in p-type base contact regions, at the same time as the drain-source implantation of p-channel MOS transistors. SOLUTION: Emitter-polysilicon layer 62 and a base Si layer 54 are etched, projecting parts 64 are left at normal positions on thick oxide regions to form base contact recovery regions, an N dopant contained in the polysilicon layer 62 diffuses slightly in an epitaxial layer 55 to form emitter regions 65, spacers 71 are formed at n-channel MOS transistors, spacers 72 are formed at the ends of the polysilicon layer 62, spacers 73 are formed at the ends of the base Si layer, the spacers 72 restricts the P injection from overdoping the extensions 64, and the base contact recovery regions are formed at the same time as forming the drain-sources of p-channel MOS transistors.

公开(公告)号：JP2000031155A

公开(公告)日：2000-01-28

申请号：JP15604999

申请日：1999-06-03

Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  DUTARTRE DIDIER ,  MONROY AUGUSTIN ,  LAURENS MICHEL ,  GUETTE FRANCOIS

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To reduce low frequency noise while sustaining accurate current amplification factor by obtaining an emitter region of single crystal silicon touching the upper layer of a stack, e.g. silicon of an upper encapsulation layer of the stack, directly on a window. SOLUTION: On a silicon substrate 1, a buried extrinsic collector layer 2 doped with n+ by implanting arsenic and two buried layers 3 similarly doped with p+ are formed and a thick n-type single crystal silicon layer 4 is grown epitaxially. Subsequently, an amorphous silicon layer 17 is deposited on a semiconductor block thus formed and etched above an oxide layer 6 to form a window 170 which is then subjected to desorption. Thereafter, a stack 8 is formed, a silicon dioxide layer 9 and a silicon nitride layer 10 are deposited thereon and then the layers 9, 10 are removed from a desired zone to obtain an emitter, i.e., an emitter window 800.

公开(公告)号：FR2779572A1

公开(公告)日：1999-12-10

申请号：FR9807059

申请日：1998-06-05

Applicant: ST MICROELECTRONICS SA

Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  DUTARTRE DIDIER ,  MONROY AUGUSTIN ,  LAURENS MICHEL ,  GUETTE FRANCOIS

IPC: H01L21/331 ,  H01L29/08 ,  H01L29/737 ,  H01L29/73 ,  H01L29/732

Abstract: A vertical bipolar transistor production process comprises epitaxy of a single crystal silicon emitter region in direct contact with the upper layer of a silicon germanium heterojunction base. Production of a vertical bipolar transistor comprises (a) forming an intrinsic collector (4) on an extrinsic collector layer buried in a semiconductor substrate (1); (b) forming a lateral insulation region (5) around the upper part of the intrinsic collector and an offset extrinsic collector well (60); (c) forming an silicon germanium heterojunction base above the intrinsic collector (4) and the lateral insulation region (5) by non-selective epitaxy of a multilayer (8) including a silicon germanium layer; and (e) forming an in-situ doped emitter by epitaxy on a window of the surface of the multilayer located above the intrinsic collector to obtain, above the window, a single crystal silicon emitter region in direct contact with the upper layer of the multilayer (8). An Independent claim is also included for a vertical bipolar transistor produced by the above process.

公开(公告)号：FR2786608B1

公开(公告)日：2001-02-09

申请号：FR9815239

申请日：1998-11-30

Applicant: ST MICROELECTRONICS SA

Inventor： LAURENS MICHEL

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

Abstract: The procedure adopts N-type epitaxy on a P-type substrate. Formation of the epitaxial layer is preceded by the formation of buried layers, and formation of the collector is carried out in a specific deep doping stage. Fabrication of a BIMOS integrated circuit comprising a NPN transistor in a strongly P-type doped wafer (42) and coated with an epitaxial lightly P-type doped layer (41) comprises: (i) forming an N-type doped well (43) constituting the collector of a bipolar transistor and having a relatively increased and substantially homogeneous doping level; (ii) coating the structure with a polycrystalline silicon layer (52) and opening this 'sandwich' above the portions of the wells of the collectors; (iii) epitaxial growth of non-doped silicon and then epitaxial growth of p-type doped silicon constituting a monocrystalline base region above the collector region; (iv) depositing an insulating layer (61) and opening it for location of the emitter; (v) depositing N-type doped polycrystalline silicon emitter (62); (vi) etching the silicon emitter outside the effective zones; (vii) etching the silicon base outside the effective zones while leaving in place a particular portion above a thick oxide region; (viii) forming spacers (72, 71,73); (ix) forming a collector contact zone (75) at the same time as implanting the drain of N channel MOS transistors; and (x) P-type implantation of the base contact outlet at the same time as implanting the drain and source of the P channel MOS transistors.

公开(公告)号：DE69936965D1

公开(公告)日：2007-10-11

申请号：DE69936965

申请日：1999-11-29

Applicant: ST MICROELECTRONICS SA

Inventor： LAURENS MICHEL

IPC: H01L21/8249 ,  H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L27/06 ,  H01L29/732

Abstract: The procedure adopts N-type epitaxy on a P-type substrate. Formation of the epitaxial layer is preceded by the formation of buried layers, and formation of the collector is carried out in a specific deep doping stage. Fabrication of a BIMOS integrated circuit comprising a NPN transistor in a strongly P-type doped wafer (42) and coated with an epitaxial lightly P-type doped layer (41) comprises: (i) forming an N-type doped well (43) constituting the collector of a bipolar transistor and having a relatively increased and substantially homogeneous doping level; (ii) coating the structure with a polycrystalline silicon layer (52) and opening this 'sandwich' above the portions of the wells of the collectors; (iii) epitaxial growth of non-doped silicon and then epitaxial growth of p-type doped silicon constituting a monocrystalline base region above the collector region; (iv) depositing an insulating layer (61) and opening it for location of the emitter; (v) depositing N-type doped polycrystalline silicon emitter (62); (vi) etching the silicon emitter outside the effective zones; (vii) etching the silicon base outside the effective zones while leaving in place a particular portion above a thick oxide region; (viii) forming spacers (72, 71,73); (ix) forming a collector contact zone (75) at the same time as implanting the drain of N channel MOS transistors; and (x) P-type implantation of the base contact outlet at the same time as implanting the drain and source of the P channel MOS transistors.

公开(公告)号：FR2779572B1

公开(公告)日：2003-10-17

申请号：FR9807059

申请日：1998-06-05

Applicant: ST MICROELECTRONICS SA

Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  DUTARTRE DIDIER ,  MONROY AUGUSTIN ,  LAURENS MICHEL ,  GUETTE FRANCOIS

IPC: H01L21/331 ,  H01L29/08 ,  H01L29/737 ,  H01L29/73 ,  H01L29/732

Abstract: A vertical bipolar transistor production process comprises epitaxy of a single crystal silicon emitter region in direct contact with the upper layer of a silicon germanium heterojunction base. Production of a vertical bipolar transistor comprises (a) forming an intrinsic collector (4) on an extrinsic collector layer buried in a semiconductor substrate (1); (b) forming a lateral insulation region (5) around the upper part of the intrinsic collector and an offset extrinsic collector well (60); (c) forming an silicon germanium heterojunction base above the intrinsic collector (4) and the lateral insulation region (5) by non-selective epitaxy of a multilayer (8) including a silicon germanium layer; and (e) forming an in-situ doped emitter by epitaxy on a window of the surface of the multilayer located above the intrinsic collector to obtain, above the window, a single crystal silicon emitter region in direct contact with the upper layer of the multilayer (8). An Independent claim is also included for a vertical bipolar transistor produced by the above process.

公开(公告)号：FR2786608A1

公开(公告)日：2000-06-02

申请号：FR9815239

申请日：1998-11-30

Applicant: ST MICROELECTRONICS SA

Inventor： LAURENS MICHEL

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

Abstract: The procedure adopts N-type epitaxy on a P-type substrate. Formation of the epitaxial layer is preceded by the formation of buried layers, and formation of the collector is carried out in a specific deep doping stage. Fabrication of a BIMOS integrated circuit comprising a NPN transistor in a strongly P-type doped wafer (42) and coated with an epitaxial lightly P-type doped layer (41) comprises: (i) forming an N-type doped well (43) constituting the collector of a bipolar transistor and having a relatively increased and substantially homogeneous doping level; (ii) coating the structure with a polycrystalline silicon layer (52) and opening this 'sandwich' above the portions of the wells of the collectors; (iii) epitaxial growth of non-doped silicon and then epitaxial growth of p-type doped silicon constituting a monocrystalline base region above the collector region; (iv) depositing an insulating layer (61) and opening it for location of the emitter; (v) depositing N-type doped polycrystalline silicon emitter (62); (vi) etching the silicon emitter outside the effective zones; (vii) etching the silicon base outside the effective zones while leaving in place a particular portion above a thick oxide region; (viii) forming spacers (72, 71,73); (ix) forming a collector contact zone (75) at the same time as implanting the drain of N channel MOS transistors; and (x) P-type implantation of the base contact outlet at the same time as implanting the drain and source of the P channel MOS transistors.