中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

68 records (took 0.022 seconds)

    LOW NOISE VERTICAL BIPOLAR TRANSISTOR AND FABRICATION THEREOF
    1.
    发明专利
    LOW NOISE VERTICAL BIPOLAR TRANSISTOR AND FABRICATION THEREOF 失效

    公开(公告)号：JP2000031155A

    公开(公告)日：2000-01-28

    申请号：JP15604999

    申请日：1999-06-03

    Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

    Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  DUTARTRE DIDIER ,  MONROY AUGUSTIN ,  LAURENS MICHEL ,  GUETTE FRANCOIS

    IPC: H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/737

    Abstract: PROBLEM TO BE SOLVED: To reduce low frequency noise while sustaining accurate current amplification factor by obtaining an emitter region of single crystal silicon touching the upper layer of a stack, e.g. silicon of an upper encapsulation layer of the stack, directly on a window. SOLUTION: On a silicon substrate 1, a buried extrinsic collector layer 2 doped with n+ by implanting arsenic and two buried layers 3 similarly doped with p+ are formed and a thick n-type single crystal silicon layer 4 is grown epitaxially. Subsequently, an amorphous silicon layer 17 is deposited on a semiconductor block thus formed and etched above an oxide layer 6 to form a window 170 which is then subjected to desorption. Thereafter, a stack 8 is formed, a silicon dioxide layer 9 and a silicon nitride layer 10 are deposited thereon and then the layers 9, 10 are removed from a desired zone to obtain an emitter, i.e., an emitter window 800.

    METHOD FOR MANUFACTURING VERTICAL BIPOLAR TRANSISTOR
    2.
    发明专利
    METHOD FOR MANUFACTURING VERTICAL BIPOLAR TRANSISTOR 失效

    公开(公告)号：JP2001196385A

    公开(公告)日：2001-07-19

    申请号：JP2000353964

    申请日：2000-11-21

    Applicant: ST MICROELECTRONICS SA

    Inventor： MARTY MICHEL ,  DUTARTRE DIDIER ,  CHANTRE ALAIN ,  JOUAN SEBASTIEN ,  LLINARES PIERRE

    IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/737

    Abstract: PROBLEM TO BE SOLVED: To propose a vertical bipolar transistor which has a reduced low-frequency noise and allowable static parameters. SOLUTION: This vertical bipolar transistor includes an intrinsic collector 4 on an extrinsic collector layer 2 buried in a semiconductor substrate, a side separation area 5 surrounding the upper part of the intrinsic collector 4, an offset extrinsic collector well 60, a base 8 which is arranged on the intrinsic collector 4 and side separation area 5 and is composed of a semiconductor area including at least one silicon layer, and two doped emitters 11 surrounded with the base 8. The emitters 11 include a first part 110 which is made of single crystal and is directly in contact with the upper surface in the predetermined window 800, and a second part 111 formed of polycrystal. These two parts are isolated by an isolated oxide layer 112 arranged at an optional distance apart from an emitter base joint part.

    EPITAXY METHOD ON SILICON SUBSTRATE INVOLVING REGIONS HEAVILY DOPED WITH BORON
    3.
    发明专利
    EPITAXY METHOD ON SILICON SUBSTRATE INVOLVING REGIONS HEAVILY DOPED WITH BORON 失效

    公开(公告)号：JP2000124132A

    公开(公告)日：2000-04-28

    申请号：JP27435199

    申请日：1999-09-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

    IPC: H01L21/302 ,  H01L21/205 ,  H01L21/22 ,  H01L21/3065 ,  H01L21/203

    Abstract: PROBLEM TO BE SOLVED: To avoid self-doping by etching a Si substrate by a specified thickness with a silicon chloride compound gas introduced before depositing in the vapor phase epitaxial deposition on the Si substrate having high-concentration dopant regions. SOLUTION: In the vapor phase epitaxial deposition on a Si substrate 1 having dopant regions 6, 7 containing boron at a high concentration, the initial annealing is selectively made and the epitaxial deposition is made for a given time to obtain an epitaxial layer 5 having a desired usual thickness. Before the epitaxial deposition, a silicon chloride compound gas is introduced to etch the Si substrate 1 by a thickness of about 100 nm or less to thereby remove a self-doped layer of boron to the epitaxial layer 5. Thus the self-doping of boron to the epitaxial layer 5 is reduced.

    Formation of single crystal semiconductor film portion separated from substrate
    4.
    发明专利
    Formation of single crystal semiconductor film portion separated from substrate 审中-公开
    形成从衬底分离的单晶半导体膜部分

    公开(公告)号：JP2007243174A

    公开(公告)日：2007-09-20

    申请号：JP2007032606

    申请日：2007-02-13

    Applicant: St Microelectronics Sa ,  エス テ マイクロエレクトロニクス エス アー

    Inventor： DUTARTRE DIDIER ,  LOUBET NICOLAS ,  TALBOT ALEXANDRE

    IPC: H01L21/762 ,  H01L21/76 ,  H01L27/12 ,  H01L29/786

    CPC classification number: H01L29/66772 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639

    Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a MOS transistor comprising a single crystal semiconductor film with no facets that is formed on a void portion, a laminated structure of single crystal thin films that prevents reduction in the device surface area, and a channel region that has a homogeneous thickness and is separated from an underlying semiconductor wafer by at least one non-single crystal layer with a homogeneous thickness.
    SOLUTION: A method of forming a single crystal semiconductor film portion separated from a substrate comprises: a step of growing a single crystal semiconductor sacrifice film 38 and a single crystal semiconductor film 40 on a single crystal semiconductor active region in an insulation region 34 by selective epitaxial growth; a step of at least partially removing the raised insulation region 34; a step of removing the single crystal semiconductor sacrifice film 38 from the side, leaving a void; and a step of filling the void with an insulator, an electrical conductor, or a heat conductor.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：为了提供一种制造包括单晶半导体膜的MOS晶体管的方法，所述单晶半导体膜没有形成在空隙部分上的小面，单晶薄膜的层压结构防止器件表面积的降低 以及具有均匀厚度并且通过至少一个均匀厚度的非单晶层与下面的半导体晶片分离的沟道区域。 解决方案：形成从衬底分离的单晶半导体膜部分的方法包括：在绝缘区域的单晶半导体有源区上生长单晶半导体牺牲膜38和单晶半导体膜40的步骤 34通过选择性外延生长; 至少部分去除凸起绝缘区域34的步骤; 从侧面去除单晶半导体牺牲膜38留下空隙的步骤; 以及用绝缘体，电导体或导热体填充空隙的步骤。 版权所有（C）2007，JPO＆INPIT

    METHOD OF DEPOSITION BY EPITAXY OF SILICON LAYER ON HIGHLY DOPED SILICON SUBSTRATE
    5.
    发明专利
    METHOD OF DEPOSITION BY EPITAXY OF SILICON LAYER ON HIGHLY DOPED SILICON SUBSTRATE 失效

    公开(公告)号：JP2000040668A

    公开(公告)日：2000-02-08

    申请号：JP13872099

    申请日：1999-05-19

    Applicant: ST MICROELECTRONICS SA

    Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

    IPC: H01L21/225 ,  H01L21/205 ,  H01L21/22 ,  H01L21/74 ,  H01L21/8249 ,  H01L27/06

    Abstract: PROBLEM TO BE SOLVED: To limit doping of a growth layer without increasing boron self-doping, by a method wherein an epitaxially grown silicon layer is deposited on a single crystalline silicon substrate that comprises zones of high concentrations of arsenic or phosphorus restraining it from being self-doped with arsenic or phosphorus. SOLUTION: Germanium compound as GeH4 gas is added in the gas phase during an annealing time from a point of time t5 to a point of time t6, a deposition process is stopped from a point, of time t6 to a point, of time t2, and a time t5 to t6 for adding a compound GeH4 is selectively set at ten seconds to tens of seconds. After Ge is deposited, hydrogen is purged for a time (tens of seconds) t6 to t2 at a temperature T1. An epitaxially grown silicon layer is self-doped for a time t3 to t4 and a block doped with arsenic and a non-doped block are formed at this deposition of Ge. Ge is deposited on a second test wafer of an epitaxially grown non-doped silicon layer for a time t5 to t6, and hydrogen is adsorbed and/or desorbed.

    PROCEDE DE DEPOT PAR EPITAXIE EN PHASE GAZEUSE
    7.
    发明专利
    PROCEDE DE DEPOT PAR EPITAXIE EN PHASE GAZEUSE 未知

    公开(公告)号：FR3057102A1

    公开(公告)日：2018-04-06

    申请号：FR1659611

    申请日：2016-10-05

    Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS CROLLES 2 SAS

    Inventor： DUTARTRE DIDIER ,  PAREDES-SAEZ VICTORIEN

    IPC: H01L21/205

    Abstract: L'invention concerne un Procédé de dépôt par épitaxie en phase gazeuse de silicium, de germanium ou de silicium-germanium sur une surface (35) semiconductrice monocristalline d'un substrat, ce procédé comprenant des étapes successives suivantes : disposer le substrat dans un réacteur d'épitaxie balayé par un gaz porteur ; porter la température du substrat à une première valeur ; introduire, pendant une première durée, au moins un premier gaz précurseur du silicium et/ou un gaz précurseur du germanium ; et réduire la température du substrat à une deuxième valeur, le procédé comprenant, à la fin de la première durée, le maintien de 1'introduction du premier gaz précurseur du silicium et/ou l'introduction d'un deuxième gaz précurseur du silicium, lesdits gaz ayant une pression partielle adaptée à former une couche de silicium ayant une épaisseur inférieure à 0, 5 nm.

Patent Agency Ranking