公开(公告)号：EP1865592A1

公开(公告)日：2007-12-12

申请号：EP06425378.4

申请日：2006-06-05

Applicant: STMicroelectronics S.r.l.

Inventor： Selgi, Lorenzo Maurizio ,  Fragapane, Leonardo ,  Arcuri, Luigi

IPC: H02M3/335 ,  H02M1/00

CPC classification number: H02M1/36 ,  H02M3/33507 ,  Y10S323/901

Abstract: An electronic power device (2) for controlling a load (3), comprising: a high-voltage integrated switch (8) having an output terminal to be connected to said load; integrated, and low-voltage driving means (9) for driving the switch (8), a start-up integrated circuit (10) comprising a high-voltage resistor (15) that can be enabled, during a step of turning on said power device (2), in order to activate the driving means. Said device is characterized in that the switch (8) and the start-up circuit (10) are integrated in a first semiconductor chip and the driving means (9) is integrated in a different, second semiconductor chip.

Abstract translation: 一种用于控制负载（3）的电子设备（2），包括：具有要连接到所述负载的输出端子的高压集成开关（8）; 集成和低电压驱动装置（9），用于驱动开关（8）;启动集成电路（10），包括可以启动的高压电阻（15），所述启动集成电路 装置（2），以激活驱动装置。 所述装置的特征在于，开关（8）和启动电路（10）集成在第一半导体芯片中，并且驱动装置（9）集成在不同的第二半导体芯片中。

公开(公告)号：EP1119104A1

公开(公告)日：2001-07-25

申请号：EP00830028.7

申请日：2000-01-20

Applicant: STMicroelectronics S.r.l.

Inventor： Grimaldi, Antonio ,  Arcuri, Luigi ,  Pisano, Salvatore

IPC: H03K17/082 ,  H03K17/0812

CPC classification number: H03K17/0822 ,  H03K17/08122

Abstract: The MOS-type power device (1) has a drain terminal (4), a source terminal (3), and a gate terminal (2), and comprises a protection circuit (11) having a first conduction terminal connected to the gate terminal (2), via a diffused resistor (5), and a second conduction terminal connected to the source terminal (3). The protection circuit (11) has a resistance variable between a first value and a second value according to the operating condition of the power device (1). A first embodiment of the protection circuit (11) comprises an ON-OFF switch (12) made by means of a horizontal MOS transistor which has a control terminal connected to the drain terminal (4) of the power device (1). A second embodiment of the protection circuit (11) envisages the replacement of the ON-OFF switch (12) with a gradual-intervention switch (23) made by means of a P-channel JFET transistor having a control terminal connected to the gate terminal (2) of the power device (1).

Abstract translation: MOS型功率器件（1）具有漏极端子（4），源极端子（3）和栅极端子（2），并且包括保护电路（11），其具有连接到栅极端子 （2），经由扩散电阻（5）和连接到源极端子（3）的第二导电端子。 根据功率器件（1）的工作状态，保护电路（11）具有在第一值和第二值之间的电阻变化。 保护电路（11）的第一实施例包括通过水平MOS晶体管制成的导通断开关（12），其具有连接到功率器件（1）的漏极端子（4）的控制端子。 保护电路（11）的第二实施例设想用通过具有连接到栅极端子的控制端子的P沟道JFET晶体管制成的逐步干预开关（23）来替换导通开关（12） （1）的电源（2）。

公开(公告)号：EP1119104B1

公开(公告)日：2009-06-17

申请号：EP00830028.7

申请日：2000-01-20

Applicant: STMicroelectronics S.r.l.

Inventor： Grimaldi, Antonio ,  Arcuri, Luigi ,  Pisano, Salvatore

IPC: H03K17/082 ,  H03K17/0812

CPC classification number: H03K17/0822 ,  H03K17/08122

公开(公告)号：EP1753022A1

公开(公告)日：2007-02-14

申请号：EP05425596.3

申请日：2005-08-12

Applicant: STMicroelectronics S.r.l.

Inventor： Miccichè, Monica ,  Grimaldi, Antonio Guiseppe ,  Arcuri, Luigi

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7811 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7802

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity, characterised in that it comprises the following steps:
- forming a first semiconductor layer (21) of the first type of conductivity and of a first resistivity (ρ 1 ) value and a first thickness (X1) on the semiconductor substrate (100),
- forming at least a second semiconductor layer (23) of a second type of conductivity and of a second resistivity (ρ 2 ) value and a second thickness (X2) on the first semiconductor layer (21),
- forming, in this at least a second semiconductor layer (23), a first plurality of implanted regions (D3) of the first type of conductivity by means of a first selective implant step with a first implant dose (Φ 3 ),
- forming implanted body regions (40) of the second type of conductivity in portions of said second semiconductor layer (23) free from said first plurality of implanted regions (D3),
- carrying out a thermal diffusion process so that the first plurality of implanted regions (D3) form a first plurality of electrically continuous implanted column regions (D) of the first type of conductivity along this at least a second semiconductor layer (23) and in electric contact with the first semiconductor layer (21), the first plurality of column implanted regions (D) delimiting a second plurality of column regions (50) of the second type of conductivity, said implanted body regions (40) resulting to be formed in said second plurality of column regions (50).

Abstract translation: 用于制造集成在第一导电类型的半导体衬底（100）上的多漏功率电子器件（30）的方法，其特征在于，该方法包括以下步骤： - 形成第一类型的第一半导体层（21） （100）上的第一电阻率（ρ1）值和第一厚度（X1）的电导率和电导率， - 形成至少第二导电类型和第二电阻率（ρ2）的第二半导体层（23） ）值和在所述第一半导体层（21）上的第二厚度（X2）， - 在该至少第二半导体层（23）中通过装置形成具有第一导电类型的第一多个注入区域（D3） （Φ3）的第一选择性注入步骤，在不具有所述第一多个注入区（D3）的所述第二半导体层（23）的部分中形成具有第二导电类型的注入体区（40） ， - 执行一个therm 以使得所述第一多个注入区域（D3）沿着该至少第二半导体层（23）形成具有第一导电类型的第一多个电连续注入列区域（D），并且与所述第一多个注入区域 第一半导体层（21），所述第一多个列注入区域（D）限定所述第二导电类型的第二多个列区域（50），所述注入体区域（40）导致形成在所述第二多个 列区域（50）。