公开(公告)号：EP1058315B1

公开(公告)日：2003-08-27

申请号：EP99830340.8

申请日：1999-06-03

Applicant: STMicroelectronics S.r.l.

Inventor： Grimaldi, Antonio ,  Schillaci, Antonino ,  Ferla, Giuseppe

IPC: H01L29/06 ,  H01L29/41

CPC classification number: H01L29/404 ,  H01L27/0629

公开(公告)号：EP1119104A1

公开(公告)日：2001-07-25

申请号：EP00830028.7

申请日：2000-01-20

Applicant: STMicroelectronics S.r.l.

Inventor： Grimaldi, Antonio ,  Arcuri, Luigi ,  Pisano, Salvatore

IPC: H03K17/082 ,  H03K17/0812

CPC classification number: H03K17/0822 ,  H03K17/08122

Abstract: The MOS-type power device (1) has a drain terminal (4), a source terminal (3), and a gate terminal (2), and comprises a protection circuit (11) having a first conduction terminal connected to the gate terminal (2), via a diffused resistor (5), and a second conduction terminal connected to the source terminal (3). The protection circuit (11) has a resistance variable between a first value and a second value according to the operating condition of the power device (1). A first embodiment of the protection circuit (11) comprises an ON-OFF switch (12) made by means of a horizontal MOS transistor which has a control terminal connected to the drain terminal (4) of the power device (1). A second embodiment of the protection circuit (11) envisages the replacement of the ON-OFF switch (12) with a gradual-intervention switch (23) made by means of a P-channel JFET transistor having a control terminal connected to the gate terminal (2) of the power device (1).

Abstract translation: MOS型功率器件（1）具有漏极端子（4），源极端子（3）和栅极端子（2），并且包括保护电路（11），其具有连接到栅极端子 （2），经由扩散电阻（5）和连接到源极端子（3）的第二导电端子。 根据功率器件（1）的工作状态，保护电路（11）具有在第一值和第二值之间的电阻变化。 保护电路（11）的第一实施例包括通过水平MOS晶体管制成的导通断开关（12），其具有连接到功率器件（1）的漏极端子（4）的控制端子。 保护电路（11）的第二实施例设想用通过具有连接到栅极端子的控制端子的P沟道JFET晶体管制成的逐步干预开关（23）来替换导通开关（12） （1）的电源（2）。

公开(公告)号：EP1058315A1

公开(公告)日：2000-12-06

申请号：EP99830340.8

申请日：1999-06-03

Applicant: STMicroelectronics S.r.l.

Inventor： Grimaldi, Antonio ,  Schillaci, Antonino ,  Ferla, Giuseppe

IPC: H01L29/06 ,  H01L29/41

CPC classification number: H01L29/404 ,  H01L27/0629

Abstract: Semiconductor device for high voltages comprising at least one power component (21) and at least one edge termination (100). Said edge termination (100) comprises a voltage divider including a plurality of capacitors (C7, C8, C9, C10, C11, C12) in series, which are formed by couples of said capacitors (C7, C8, C9, C10, C11, C12) formed by metal layers (71; 72) of a first level and polysilicon layers (11) of a second level interposed from a dielectric layer (8) underlying said metal layers (71; 72). The metal layers (71; 72) are alternated to said polysilicon layers (11) but extend in part over a zone of said dielectric layer (8) superimposed on said polysilicon layers (11). The edge termination (100) is connected between non-driveable terminals of said power component (21).

Abstract translation: 用于高电压的半导体器件包括至少一个功率部件（21）和至少一个边缘终端（100）。 所述边缘终端（100）包括分压器，其包括串联的多个电容器（C7，C8，C9，C10，C11，C12），所述电容器由所述电容器（C7，C8，C9，C10，C11， 由第一级的金属层（71; 72）形成的第二层的第二层（11）和从第一层的介电层（8）介入的第二层的多晶硅层（11）形成。 金属层（71; 72）与所述多晶硅层（11）交替，但部分地跨越叠加在所述多晶硅层（11）上的所述介电层（8）的区域。 边缘终端（100）连接在所述功率部件（21）的不可驱动端子之间。

公开(公告)号：EP1119104B1

公开(公告)日：2009-06-17

申请号：EP00830028.7

申请日：2000-01-20

Applicant: STMicroelectronics S.r.l.

Inventor： Grimaldi, Antonio ,  Arcuri, Luigi ,  Pisano, Salvatore

IPC: H03K17/082 ,  H03K17/0812

CPC classification number: H03K17/0822 ,  H03K17/08122

公开(公告)号：EP1058318A1

公开(公告)日：2000-12-06

申请号：EP99830339.0

申请日：1999-06-03

Applicant: STMicroelectronics S.r.l.

Inventor： Schillaci, Antonino ,  Grimaldi, Antonio ,  Ferla, Giuseppe

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/41 ,  H01L29/06

CPC classification number: H01L29/404 ,  H01L27/088 ,  H01L29/7811

Abstract: Semiconductor device for high voltages comprising at least one power component (21), e.g. a power MOSFET, and at least one edge termination (100). Said edge termination (100) comprises a voltage divider including a plurality of diode-connected MOS transistors (31;32;33;34) in series, said edge termination (100) being connected between current-carrying, main terminals of said power component (21).

Abstract translation: 用于高电压的半导体器件包括至少一个功率部件（21），例如， 功率MOSFET和至少一个边缘终端（100）。 所述边缘终端（100）包括一个分压器，包括串联的多个二极管连接的MOS晶体管（31; 32; 33; 34），所述边缘终端（100）连接在所述功率部件的载流主端子 （21）。

公开(公告)号：EP1058318B1

公开(公告)日：2008-04-16

申请号：EP99830339.0

申请日：1999-06-03

Applicant: STMicroelectronics S.r.l.

Inventor： Schillaci, Antonino ,  Grimaldi, Antonio ,  Ferla, Giuseppe

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/41 ,  H01L29/06

CPC classification number: H01L29/404 ,  H01L27/088 ,  H01L29/7811

公开(公告)号：EP0782201B1

公开(公告)日：2000-08-30

申请号：EP95830542.7

申请日：1995-12-28

Applicant: STMicroelectronics S.r.l. ,  Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno

Inventor： Grimaldi, Antonio ,  Schillaci, Antonino ,  Frisina, Ferruccio ,  Ferla, Giuseppe

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/423 ,  H01L29/417 ,  H01L23/482 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7802 ,  H01L23/4824 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41725 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A MOS-technology power device integrated structure comprises a plurality of elementary functional units formed in a semiconductor material layer (3) of a first conductivity type. The elementary functional units comprise body stripes (9;90) of a second conductivity type extending substantially parallely to each other and source regions (14;140) of the first conductivity type. A conductive gate layer (17;170) is insulatively disposed over the semiconductor material layer (3) between the body stripes (9;90). A mesh (4;40) of the second conductivity type is formed in the semiconductor material layer (3) and comprises an annular frame region (5;50) surrounding the plurality of body stripes (9;90) and at least one first elongated stripe (7;60) extending within the annular frame region (5;50) in a direction substantially orthogonal to the body stripes (9;90) and merged with the annular frame region (5;50), the body stripes (9;90) being divided by the first elongated stripe (7;60) in two respective groups and being merged with the mesh (4;40). A conductive gate finger (25;250) connected to said conductive gate layer (17;170) insulatively extends over the first elongated stripe (7;60). Source metal plates (20;200) are provided covering each group of parallel body stripes and contacting each body stripe of the group. The conductive gate finger (25;250) is covered and contacted by a respective metal gate finger (27;270).