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    A system for the complete diagnosis of a driver
    4.
    发明公开
    A system for the complete diagnosis of a driver 有权
    Einrichtung zurvollständigen诊断eine Treibers

    公开(公告)号：EP1052518A1

    公开(公告)日：2000-11-15

    申请号：EP99830294.7

    申请日：1999-05-13

    Applicant: STMicroelectronics S.r.l. ,  MAGNETI MARELLI S.p.A.

    Inventor： Milanesi, Andrea ,  Chicca, Stefania ,  Poletto, Vanni ,  Giorgetta, Valerio ,  Sgatti, Stefano ,  Vigna, Sergio

    IPC: G01R31/02

    CPC classification number: G01R31/024

    Abstract: A system is described for the diagnosis of a driver (D) of the type adapted to detect one or more circuit anomalies which can occur in the said driver, including:

    voltage comparator circuits (10, 20) adapted to generate diagnostic logic signals (F 1 , F 2 , F 3 ) each indicative of the existence of a corresponding type of anomaly; and
    a coding circuit (M, SM) adapted to receive these diagnostic signals (F 1 , F 2 , F 3 ) and to output information relating to an overall operating state of the circuit. The coding circuit (M, SM) includes a first portion adapted to provide at its output first logic signals (SHB, SHG, OL) indicative of the last anomaly occurred since a system reset operation, and a second portion for coding such first logic signals (SHB, SHG, OL). The second portion includes a sequential logic network (SM) adapted to:


    receive the first logic input signals (SHB, SHG, OL) and at least one second logic signal (IN) indicative of the current operating phase of the driver (D); and
    achieve, as a function of the said first and second logic signals (SHB, SHG, OL; IN) a stable internal state such as to determine at the output information in the form of an N bit coded word representative of an occurred anomaly, of a condition of absence of anomaly in the current operating phase, or of a condition of absence of anomaly in any operating phase.

    Abstract translation: 描述了用于诊断适于检测可能发生在所述驱动器中的一个或多个电路异常的类型的驱动器（D）的系统，包括：适于产生诊断逻辑信号的电压比较器电路（10,20）（F1 ，F2，F3），每个指示存在相应类型的异常; 以及适于接收这些诊断信号（F1，F2，F3）的编码电路（M，SM），并且输出与电路的总体工作状态有关的信息。 编码电路（M，SM）包括适于在其输出端提供指示自系统复位操作以来发生的最后异常的第一逻辑信号（SHB，SHG，OL）的第一部分和用于对这些第一逻辑信号进行编码的第二部分 （SHB，SHG，OL）。 第二部分包括适于：接收第一逻辑输入信号（SHB，SHG，OL）的顺序逻辑网络（SM）和指示驾驶员（D）的当前操作阶段的至少一个第二逻辑信号（IN）; 并且作为所述第一和第二逻辑信号（SHB，SHG，OL; IN）的函数实现稳定的内部状态，例如以表示发生的异常的N位编码字的形式在输出信息处确定， 在当前运行阶段没有异常的情况，或任何运行阶段没有异常的情况。

    Bidirectional electronic switch
    5.
    发明公开
    Bidirectional electronic switch 失效
    Elektronischer Zweirichtungsschalter

    公开(公告)号：EP0954079A1

    公开(公告)日：1999-11-03

    申请号：EP98830252.7

    申请日：1998-04-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Milanesi, Andrea ,  Chicca, Stefania ,  Morelli, Marco ,  Poletto, Vanni

    IPC: H02H1/00 ,  G01R31/00 ,  H03K17/082

    CPC classification number: H03K17/0822

    Abstract: A guard circuit of a diagnostic output line (K-line) of a control unit (ECU) in the event of a ground (GND) disconnection or of a "below ground" condition, where the diagnostic output line (K-line) comprises a first interface DMOS transistor (MI) with a source connected to ground and a drain coupled to the diagnostic output lines (VOUT) through a second DMOS transistor (MP) with a source connected to the output line (VOUT) and a drain connected to the source of the first DMOS transistor (MI), a comparator (COMP) of the voltage (VOUT) of the diagnostic output line with the potential of the ground node (GND), a two-input logic (AND) gate (A1), with an input connected to the output of the comparator (COMP) and the other input coupled to the gate of said first DMOS transistor (MI), whose output controls a current generator (I) forcing a current, limited by a resistor (R), on the diagnostic output line (VOUT), the gate of the second DMOS transistor (MP) being coupled to the connection node between the generator (I) and the limiting resistor (R), employs a third MOS transistor (M) for switching off the second DMOS transistor (MP), functionally coupled in parallel to the resistor (R) and controlled by a line comprising a second current generator (I 1 ) controlled through an inverter (INV) by the output of the comparator (COMP) and forcing a current through a voltage divider (R 1 , R 2 ) on said diagnostic output line (VOUT). The intermediate node of the voltage divider is coupled to a gate of the third MOS transistor (M), and a third current generator (I 2 ) connected between the gate of the third transistor (M) and ground is controlled by the output of the comparator (COMP) in phase to the first current generator (I) and in phase opposition to the second current generator (I 1 ).

    Abstract translation: 在诊断输出线（K线）包括地面（GND）断开或“低于地面”状态的情况下，控制单元（ECU）的诊断输出线（K线）的保护电路 源极连接到地的第一接口DMOS晶体管（MI）和通过连接到输出线（VOUT）的源极的第二DMOS晶体管（MP）耦合到诊断输出线（VOUT）的漏极，以及漏极连接到 第一DMOS晶体管（MI）的源极，具有接地节点（GND）的电位的诊断输出线的电压（VOUT）的比较器（COMP），双输入逻辑（AND）门（A1） ，其中输入连接到比较器（COMP）的输出端，而另一个输入端耦合到所述第一DMOS晶体管（MI）的栅极，其输出控制电流发生器（I），该电流发生器（I）由电阻器（R ），在诊断输出线（VOUT）上，第二DMOS晶体管（MP）的栅极耦合到连接节点 在发生器（I）和限制电阻器（R）之间使用用于关断第二DMOS晶体管（MP）的第三MOS晶体管（M），其功能上与电阻器（R）并联并且由包括 通过比较器（COMP）的输出通过反相器（INV）控制第二电流发生器（I1），并强制通过所述诊断输出线（VOUT）上的分压器（R1，R2）的电流。 分压器的中间节点耦合到第三MOS晶体管（M）的栅极，并且连接在第三晶体管（M）的栅极与地之间的第三电流发生器（I2）由比较器的输出端控制 （COMP）与第一电流发生器（I）同相并且与第二电流发生器（I1）相反。

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