公开(公告)号：EP1113492A1

公开(公告)日：2001-07-04

申请号：EP99830826.6

申请日：1999-12-31

Applicant: STMicroelectronics S.r.l. ,  CNR-IMETEM

Inventor： D'Arrigo, Giuseppe ,  Spinella, Corrado ,  Coffa, Salvatore ,  Arena, Giuseppe ,  Camalleri, Marco

IPC: H01L21/762 ,  H01L21/316

CPC classification number: H01L21/3063 ,  C25F3/12 ,  H01L21/31662 ,  H01L21/32105 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76286

Abstract: This invention relates to a method of fabricating a SOI (Silicon-On-Insulator) wafer suitable to manufacture electronic semiconductor devices and including a substrate of monocrystalline silicon with a top surface, and a doped buried region in the substrate. The method comprises at least one step of forming trench-like openings extended from the substrate surface down to the buried region, and comprises:

a selective etching step carried out through said openings to change said buried region of monocrystalline silicon into porous silicon;
a subsequent step of oxidising the buried region that has been changed into porous silicon, to obtain an insulating portion of said SOI wafer.

Abstract translation: 本发明涉及一种制造适合于制造电子半导体器件并包括具有顶表面的单晶硅衬底以及衬底中的掺杂掩埋区的SOI（绝缘体上硅）晶片的方法。 该方法包括形成从衬底表面向下延伸到掩埋区域的沟槽状开口的至少一个步骤，并且包括：通过所述开口执行的选择性蚀刻步骤，以将所述单晶硅的掩埋区域改变为多孔硅; 氧化已经变成多孔硅的掩埋区域的后续步骤，以获得所述SOI晶片的绝缘部分。

公开(公告)号：EP1113492B1

公开(公告)日：2009-09-23

申请号：EP99830826.6

申请日：1999-12-31

Applicant: STMicroelectronics S.r.l.

Inventor： D'Arrigo, Giuseppe ,  Spinella, Corrado ,  Coffa, Salvatore ,  Arena, Giuseppe ,  Camalleri, Marco

IPC: H01L21/762 ,  H01L21/316

CPC classification number: H01L21/3063 ,  C25F3/12 ,  H01L21/31662 ,  H01L21/32105 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76286

公开(公告)号：EP1258937A1

公开(公告)日：2002-11-20

申请号：EP01830314.9

申请日：2001-05-17

Applicant: STMicroelectronics S.r.l.

Inventor： D'Arrigo, Giuseppe ,  Coffa, Salvatore ,  Spinella, Rosario Corrado

IPC: H01M8/10 ,  H01M8/24

CPC classification number: H01M8/241 ,  H01M8/1004 ,  H01M8/1007 ,  H01M2300/0082

Abstract: A miniscule fuel cell is realized on a doped monocrystalline silicon subtrate.
The microporous catalytic electrodes permeable to a gaseous fuel or an oxygen containing gas are constituted by a plurality of coplanar and parallel strips (3,4) of a catalytic metallic material electroplated or sputtered over an heterogeneous columnar skeleton structure of monocrystalline silicon (1,2) purposely formed by etching the silicon substrate to realize the plurality of parallel trenches (7,8) for ducting reagent and products of the electrode reactions to and from the microporous catalytic electrode formed thereon.
The spaced parallel strips (3,4) constituting the microporous catalytic electrode permeable to gases are electrically connected one to the other by parallel strips (5,6) of conducting material alternate to the microporous strips of catalytic electrode material. The whole composite electrode structure of the half-cell is in electrical contact with the conducting substrate of monocrystalline silicon in correspondence of said strips of conducting material deposited over the crests of separation between adjacent parallel trenches etched in the silicon substrate, and optionally also in correspondence of the heterogeneous columnar skeleton of conducting monocrystalline silicon in case it is not completely removed by an eventual chemical and/or electrochemical final etching step after having deposited thereon the catalytic metal to form a self-sustaining microporous structure.
Two half-cells thus formed on distinct silicon substrates are thereafter placed one against the other sandwiching, at least over the cell area, a thin film of permionic membrane substantially impermeable to fluids.

Abstract translation: 甲微乎其微燃料电池实现上的掺杂单晶硅subtrate。 可渗透气体燃料或以含氧气体的微孔催化电极通过电镀的催化金属材料的共面和带（3,4）的多元构成或溅射在单晶硅的异质柱状骨架结构（平行1.2 ）特意通过蚀刻硅衬底来实现平行沟槽（7,8），用于管道的电极反应的试剂和产品，和从在其上形成微多孔催化电极的多个形成。 构成微多孔催化电极透过气体隔开的平行条带（3,4）被电连接一个到另一个由导电材料的替代品催化电极材料的微孔条带的平行条带（5,6）。 半电池的整个复合电极结构与单晶硅在进行淀积在硅衬底蚀刻相邻平行沟槽之间的分离的齿顶材料的所述条带的对应的导电衬底电接触，并由此任选地在对应 在情况下进行的单晶硅的异质柱状骨架的它没有完全呼叫通过在最终的化学和/或电化学蚀刻最后一步在其上的催化金属具有沉积以形成自持微孔结构之后去除。 此后两个半电池由此形成不同硅衬底上放置一个抵靠另一个夹持，至少在小区区域，permionic膜的薄膜基本上不渗透流体。

公开(公告)号：EP1113492B9

公开(公告)日：2010-02-03

申请号：EP99830826.6

申请日：1999-12-31

Applicant: STMicroelectronics S.r.l.

Inventor： D'Arrigo, Giuseppe ,  Spinella, Corrado ,  Coffa, Salvatore ,  Arena, Giuseppe ,  Camalleri, Marco

IPC: H01L21/762 ,  H01L21/316

CPC classification number: H01L21/3063 ,  C25F3/12 ,  H01L21/31662 ,  H01L21/32105 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76286

公开(公告)号：EP1493711B1

公开(公告)日：2008-04-16

申请号：EP03425441.7

申请日：2003-07-04

Applicant: STMicroelectronics S.r.l.

Inventor： D'Arrigo, Giuseppe ,  Spinella, Rosario Corrado

IPC: B81B3/00

CPC classification number: B81C1/00142 ,  B81B2201/042 ,  B81C2201/0115

公开(公告)号：EP1493711A1

公开(公告)日：2005-01-05

申请号：EP03425441.7

申请日：2003-07-04

Applicant: STMicroelectronics S.r.l.

Inventor： D'Arrigo, Giuseppe ,  Spinella, Rosario Corrado

IPC: B81B3/00

CPC classification number: B81C1/00142 ,  B81B2201/042 ,  B81C2201/0115

Abstract: The present invention refers to a process for the obtainment of a semiconductor comprising a suspended micro-system, to a device so obtained and its applications.
In one embodiment the process for the obtainment of a semiconductor device comprising a suspended micro-system comprises the phases of: forming a silicon substrate (10); forming a silicon porous layer (11) above said substrate (10); oxidizing said porous layer (12); depositing on the whole device an oxide layer (13); depositing above said oxide layer (13) a first polysilicon layer (14); removing selectively said first polysilicon layer (14), said oxide layer (13) and said porous layer (12); depositing on the whole device a nitride layer (16); depositing on the whole device a second polysilicon layer (17); removing selectively said second polysilicon layer (17), said nitride layer (16), said first polysilicon layer (14), and said oxide layer (13); removing said porous layer (12) in the areas made accessible by the preceding phase.