公开(公告)号：EP1659637A3

公开(公告)日：2006-07-19

申请号：EP05025287.3

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Arena, Giuseppe ,  Ferla, Giuseppe ,  Camalleri, Marco

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336 ,  H01L21/28

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712

Abstract: The invention relates to a process for the realisation of a high integration density power MOS device comprising the following steps of:

providing a doped semiconductor substrate (10) with a first type of conductivity (N);
forming, on the substrate (10), a semiconductor layer (11) with lower conductivity (N-);
forming, on the semiconductor layer (11), a dielectric layer (16) of thickness comprised between 3000 and 13000 A (Angstrom);
depositing, on the dielectric layer (16), a hard mask layer;
masking the hard mask layer by means of a masking layer;
etching the hard mask layers and the underlying dielectric layer (16) for defining a plurality of hard mask portions (19) to protect said dielectric layer (16);
removing the masking layer;
isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer (16) below said hard mask portions (19);
forming a gate oxide (15) of thickness comprised between 150 and 1500 A (Angstrom)
depositing a conductor material (24) in said cavities and above the same to form a recess spacer (20), which is totally aligned with a gate structure (14) comprising said thick dielectric layer (16) and said gate oxide (15).

公开(公告)号：EP1113492A1

公开(公告)日：2001-07-04

申请号：EP99830826.6

申请日：1999-12-31

Applicant: STMicroelectronics S.r.l. ,  CNR-IMETEM

Inventor： D'Arrigo, Giuseppe ,  Spinella, Corrado ,  Coffa, Salvatore ,  Arena, Giuseppe ,  Camalleri, Marco

IPC: H01L21/762 ,  H01L21/316

CPC classification number: H01L21/3063 ,  C25F3/12 ,  H01L21/31662 ,  H01L21/32105 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76286

Abstract: This invention relates to a method of fabricating a SOI (Silicon-On-Insulator) wafer suitable to manufacture electronic semiconductor devices and including a substrate of monocrystalline silicon with a top surface, and a doped buried region in the substrate. The method comprises at least one step of forming trench-like openings extended from the substrate surface down to the buried region, and comprises:

a selective etching step carried out through said openings to change said buried region of monocrystalline silicon into porous silicon;
a subsequent step of oxidising the buried region that has been changed into porous silicon, to obtain an insulating portion of said SOI wafer.

Abstract translation: 本发明涉及一种制造适合于制造电子半导体器件并包括具有顶表面的单晶硅衬底以及衬底中的掺杂掩埋区的SOI（绝缘体上硅）晶片的方法。 该方法包括形成从衬底表面向下延伸到掩埋区域的沟槽状开口的至少一个步骤，并且包括：通过所述开口执行的选择性蚀刻步骤，以将所述单晶硅的掩埋区域改变为多孔硅; 氧化已经变成多孔硅的掩埋区域的后续步骤，以获得所述SOI晶片的绝缘部分。

公开(公告)号：EP2302684A3

公开(公告)日：2012-03-14

申请号：EP10011934.6

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Arena, Giuseppe ,  Camalieri, Marco ,  Ferla, Giuseppe

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336 ,  H01L21/28

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712

Abstract: The invention relates to a high integration density power MOS device comprising a substrate (10) of a doped semiconductor with a first type of conductivity whereon a semiconductor layer (11) with lower conductivity is formed, transistor elementary structures Ti (i=l..n) comprising body regions (12), arranged above in said semiconductor (11) inside which the source regions (13) are confined; the power MOS device comprises in each of the transistor elementary structures Ti (i=1..n) a gate structure (14) of the type with dual thickness comprising a first thin layer (15) of gate oxide onto which, at least partially, a dielectric layer (17) is overlapped having thickness greater than said first thin layer (15) and defining a central portion (17) delimited by lateral portions (18) of conductive material, said gate structure (14) further comprising a nitride upper portion (19) above the thick dielectric layer (17) and said lateral portions (18) of conductor material.

公开(公告)号：EP1659637A2

公开(公告)日：2006-05-24

申请号：EP05025287.3

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Arena, Giuseppe ,  Ferla, Giuseppe ,  Camalleri, Marco

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336 ,  H01L21/28

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712

Abstract: The invention relates to a process for the realisation of a high integration density power MOS device comprising the following steps of:

providing a doped semiconductor substrate (10) with a first type of conductivity (N);
forming, on the substrate (10), a semiconductor layer (11) with lower conductivity (N-);
forming, on the semiconductor layer (11), a dielectric layer (16) of thickness comprised between 3000 and 13000 A (Angstrom);
depositing, on the dielectric layer (16), a hard mask layer;
masking the hard mask layer by means of a masking layer;
etching the hard mask layers and the underlying dielectric layer (16) for defining a plurality of hard mask portions (19) to protect said dielectric layer (16);
removing the masking layer;
isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer (16) below said hard mask portions (19);
forming a gate oxide (15) of thickness comprised between 150 and 1500 A (Angstrom)
depositing a conductor material (24) in said cavities and above the same to form a recess spacer (20), which is totally aligned with a gate structure (14) comprising said thick dielectric layer (16) and said gate oxide (15).

Abstract translation: 本发明涉及一种实现高集成度功率MOS器件的方法，包括以下步骤：提供具有第一导电类型（N）的掺杂半导体衬底（10）; 在衬底（10）上形成具有较低导电性（N-）的半导体层（11）; 在半导体层（11）上形成厚度介于3000和13000A（埃）之间的介电层（16）; 在电介质层（16）上沉积硬掩模层; 借助掩模层掩蔽硬掩模层; 刻蚀所述硬掩模层和所述下层电介质层（16）以限定多个硬掩模部分（19）以保护所述电介质层（16）; 去除掩模层; 各向同性和横向蚀刻所述介质层，在所述硬掩模部分（19）下方的所述介质层（16）中形成横向腔; 形成厚度在150与1500埃（埃）之间的栅极氧化物（15），在所述空腔中沉积导体材料（24）并在其上方形成凹槽隔离物（20），该凹陷隔离物（20）与栅极结构 14）包括所述厚介电层（16）和所述栅极氧化物（15）。

公开(公告)号：EP1113492B1

公开(公告)日：2009-09-23

申请号：EP99830826.6

申请日：1999-12-31

Applicant: STMicroelectronics S.r.l.

Inventor： D'Arrigo, Giuseppe ,  Spinella, Corrado ,  Coffa, Salvatore ,  Arena, Giuseppe ,  Camalleri, Marco

IPC: H01L21/762 ,  H01L21/316

CPC classification number: H01L21/3063 ,  C25F3/12 ,  H01L21/31662 ,  H01L21/32105 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76286

公开(公告)号：EP1742257A1

公开(公告)日：2007-01-10

申请号：EP05425483.4

申请日：2005-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Arena, Giuseppe ,  Donato, Caterina ,  Camalleri, Cateno Marco ,  Magri, Angelo

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/511 ,  H01L29/66734

Abstract: A trench (5) is formed in a semiconductor body (2); the side walls and the bottom of the trench are covered with a first dielectric material layer (9); the trench (5) is filled with a second dielectric material layer (10); the first and the second dielectric material layers (9, 10) are etched via a partial, simultaneous and controlled etching such that the dielectric materials have similar etching rates; a gate-oxide layer (13) having a thickness smaller than the first dielectric material layer (9) is deposited on the walls of the trench (5); a gate region (14) of conductive material is formed within the trench (5); and body regions (7) and source regions (8) are formed within the semiconductor body (2), at the sides of and insulated from the gate region (14). Thereby, the gate region (14) extends only on top of the remaining portions of the first and second dielectric material layers (9, 10).

Abstract translation: 沟槽（5）形成在半导体本体（2）中; 沟槽的侧壁和底部被第一介电材料层（9）覆盖; 沟槽（5）填充有第二电介质层（10）; 通过部分，同时和受控的蚀刻蚀刻第一和第二介电材料层（9,10），使得介电材料具有相似的蚀刻速率; 在沟槽（5）的壁上沉积具有小于第一介电材料层（9）的厚度的栅极 - 氧化物层（13）。 在沟槽（5）内形成导电材料的栅区（14）; 并且在半导体本体（2）中，在栅极区域（14）的侧面和与栅极区域（14）绝缘的位置上形成有主体区域（7）和源极区域（8）。 因此，栅极区域（14）仅在第一和第二介电材料层（9,10）的剩余部分的顶部延伸。

公开(公告)号：EP1427011A1

公开(公告)日：2004-06-09

申请号：EP02425746.1

申请日：2002-12-04

Applicant: STMicroelectronics S.r.l.

Inventor： D'Arrigo, Giuseppe Alessio Maria ,  Spinella, Rosario Corrado ,  Arena, Giuseppe ,  Lorenti, Simona

IPC: H01L21/764 ,  H01L21/306 ,  H01L21/3065 ,  B81C1/00

CPC classification number: B81C1/00507 ,  G01N27/447 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764

Abstract: The present invention describes a process for realizing buried microchannels (10) in an integrated structure (1) comprising a monocrystalline silicon substrate (2).
Advantageously, according to the invention, the process provides to form in the substrate (2) at least one trench (4) and to obtain microchannels (10) starting from a deep cavity characterised by a small surface port obtained through anisotropic etching of the at least one trench (4).
Microchannels (10) are completely buried in the substrate (2) in a completely microcrystalline structure.

Abstract translation: 本发明描述了在包括单晶硅衬底（2）的集成结构（1）中实现埋入式微通道（10）的方法。 有利地，根据本发明，该方法提供在衬底（2）中形成至少一个沟槽（4）并且从深空腔开始获得微通道（10），其特征在于通过各向异性获得的小表面端口 蚀刻所述至少一个沟槽（4）。 微通道（10）以完全微晶结构完全掩埋在基板（2）中。

公开(公告)号：EP2302684A2

公开(公告)日：2011-03-30

申请号：EP10011934.6

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Arena, Giuseppe ,  Camalieri, Marco ,  Ferla, Giuseppe

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336 ,  H01L21/28

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712

Abstract: The invention relates to a high integration density power MOS device comprising a substrate (10) of a doped semiconductor with a first type of conductivity whereon a semiconductor layer (11) with lower conductivity is formed, transistor elementary structures Ti (i=l..n) comprising body regions (12), arranged above in said semiconductor (11) inside which the source regions (13) are confined; the power MOS device comprises in each of the transistor elementary structures Ti (i=1..n) a gate structure (14) of the type with dual thickness comprising a first thin layer (15) of gate oxide onto which, at least partially, a dielectric layer (17) is overlapped having thickness greater than said first thin layer (15) and defining a central portion (17) delimited by lateral portions (18) of conductive material, said gate structure (14) further comprising a nitride upper portion (19) above the thick dielectric layer (17) and said lateral portions (18) of conductor material.

Abstract translation: 本发明涉及一种高集成度功率MOS器件，其包括具有第一导电类型的掺杂半导体的衬底（10），其中形成具有较低导电性的半导体层（11），晶体管元素结构Ti（i = n）包括主体区域（12），其布置在所述半导体（11）的上方，所述源极区域（13）被限制在所述半导体内部; 功率MOS器件在晶体管单元结构Ti（i = 1.n）的每一个中包括具有双重厚度的类型的栅极结构（14），其包括栅极氧化物的第一薄层（15），至少部分 ，电介质层（17）重叠，其厚度大于所述第一薄层（15），并且限定由导电材料的横向部分（18）限定的中心部分（17），所述栅极结构（14）还包括氮化物层 在厚介电层（17）和导体材料的所述横向部分（18）之上的部分（19）。

公开(公告)号：EP1113492B9

公开(公告)日：2010-02-03

申请号：EP99830826.6

申请日：1999-12-31

Applicant: STMicroelectronics S.r.l.

Inventor： D'Arrigo, Giuseppe ,  Spinella, Corrado ,  Coffa, Salvatore ,  Arena, Giuseppe ,  Camalleri, Marco

IPC: H01L21/762 ,  H01L21/316

CPC classification number: H01L21/3063 ,  C25F3/12 ,  H01L21/31662 ,  H01L21/32105 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76286

公开(公告)号：EP1427011B1

公开(公告)日：2008-09-10

申请号：EP02425746.1

申请日：2002-12-04

Applicant: STMicroelectronics S.r.l.

Inventor： D'Arrigo, Giuseppe Alessio Maria ,  Spinella, Rosario Corrado ,  Arena, Giuseppe ,  Lorenti, Simona

IPC: H01L21/764 ,  H01L21/306 ,  H01L21/3065 ,  B81C1/00

CPC classification number: B81C1/00507 ,  G01N27/447 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764