公开(公告)号：EP1659637A2

公开(公告)日：2006-05-24

申请号：EP05025287.3

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Arena, Giuseppe ,  Ferla, Giuseppe ,  Camalleri, Marco

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336 ,  H01L21/28

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712

Abstract: The invention relates to a process for the realisation of a high integration density power MOS device comprising the following steps of:

providing a doped semiconductor substrate (10) with a first type of conductivity (N);
forming, on the substrate (10), a semiconductor layer (11) with lower conductivity (N-);
forming, on the semiconductor layer (11), a dielectric layer (16) of thickness comprised between 3000 and 13000 A (Angstrom);
depositing, on the dielectric layer (16), a hard mask layer;
masking the hard mask layer by means of a masking layer;
etching the hard mask layers and the underlying dielectric layer (16) for defining a plurality of hard mask portions (19) to protect said dielectric layer (16);
removing the masking layer;
isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer (16) below said hard mask portions (19);
forming a gate oxide (15) of thickness comprised between 150 and 1500 A (Angstrom)
depositing a conductor material (24) in said cavities and above the same to form a recess spacer (20), which is totally aligned with a gate structure (14) comprising said thick dielectric layer (16) and said gate oxide (15).

Abstract translation: 本发明涉及一种实现高集成度功率MOS器件的方法，包括以下步骤：提供具有第一导电类型（N）的掺杂半导体衬底（10）; 在衬底（10）上形成具有较低导电性（N-）的半导体层（11）; 在半导体层（11）上形成厚度介于3000和13000A（埃）之间的介电层（16）; 在电介质层（16）上沉积硬掩模层; 借助掩模层掩蔽硬掩模层; 刻蚀所述硬掩模层和所述下层电介质层（16）以限定多个硬掩模部分（19）以保护所述电介质层（16）; 去除掩模层; 各向同性和横向蚀刻所述介质层，在所述硬掩模部分（19）下方的所述介质层（16）中形成横向腔; 形成厚度在150与1500埃（埃）之间的栅极氧化物（15），在所述空腔中沉积导体材料（24）并在其上方形成凹槽隔离物（20），该凹陷隔离物（20）与栅极结构 14）包括所述厚介电层（16）和所述栅极氧化物（15）。

公开(公告)号：EP1113492B9

公开(公告)日：2010-02-03

申请号：EP99830826.6

申请日：1999-12-31

Applicant: STMicroelectronics S.r.l.

Inventor： D'Arrigo, Giuseppe ,  Spinella, Corrado ,  Coffa, Salvatore ,  Arena, Giuseppe ,  Camalleri, Marco

IPC: H01L21/762 ,  H01L21/316

CPC classification number: H01L21/3063 ,  C25F3/12 ,  H01L21/31662 ,  H01L21/32105 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76286

公开(公告)号：EP1455397A3

公开(公告)日：2005-08-17

申请号：EP03029916.8

申请日：2003-12-29

Applicant: STMicroelectronics S.r.l.

Inventor： Magri', Angelo ,  Frisina, Feruccio ,  Ferla, Giuseppe ,  Camalleri, Marco

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66712

Abstract: The invention relates to a vertical-conduction and planar-structure MOS device having a double thickness of gate oxide comprising a first portion (5a) of gate oxide having a lower thickness in a channel area close to the active areas (4), and a second portion (5b) of thicker gate oxide in a central area (11) on a JFET area and an enrichment region (9) in the JFET area under the second . portion (5b) of thicker gate oxide (11).
The invention also relates to a method for realising on a semiconductor substrate (2) MOS transistor electronic devices (1) with improved static and dynamic performances and high scaling down density, these transistors having traditional active areas (4) defined in the substrate (2) at the periphery of a channel region whereon a gate region is realised. The method provides at least the following steps: realising the MOS transistor starting from a planar structure with a double thickness of gate oxide comprising a thin layer in the channel area close to the active areas (4) and a thicker layer in the central area (11) on the channel; and realising an enrichment region (9) in the JFET area below the thicker layer.

公开(公告)号：EP1113492B1

公开(公告)日：2009-09-23

申请号：EP99830826.6

申请日：1999-12-31

Applicant: STMicroelectronics S.r.l.

Inventor： D'Arrigo, Giuseppe ,  Spinella, Corrado ,  Coffa, Salvatore ,  Arena, Giuseppe ,  Camalleri, Marco

IPC: H01L21/762 ,  H01L21/316

CPC classification number: H01L21/3063 ,  C25F3/12 ,  H01L21/31662 ,  H01L21/32105 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76286

公开(公告)号：EP1659637A3

公开(公告)日：2006-07-19

申请号：EP05025287.3

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Arena, Giuseppe ,  Ferla, Giuseppe ,  Camalleri, Marco

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336 ,  H01L21/28

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66712

Abstract: The invention relates to a process for the realisation of a high integration density power MOS device comprising the following steps of:

providing a doped semiconductor substrate (10) with a first type of conductivity (N);
forming, on the substrate (10), a semiconductor layer (11) with lower conductivity (N-);
forming, on the semiconductor layer (11), a dielectric layer (16) of thickness comprised between 3000 and 13000 A (Angstrom);
depositing, on the dielectric layer (16), a hard mask layer;
masking the hard mask layer by means of a masking layer;
etching the hard mask layers and the underlying dielectric layer (16) for defining a plurality of hard mask portions (19) to protect said dielectric layer (16);
removing the masking layer;
isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer (16) below said hard mask portions (19);
forming a gate oxide (15) of thickness comprised between 150 and 1500 A (Angstrom)
depositing a conductor material (24) in said cavities and above the same to form a recess spacer (20), which is totally aligned with a gate structure (14) comprising said thick dielectric layer (16) and said gate oxide (15).

公开(公告)号：EP1455397A2

公开(公告)日：2004-09-08

申请号：EP03029916.8

申请日：2003-12-29

Applicant: STMicroelectronics S.r.l.

Inventor： Magri', Angelo ,  Frisina, Feruccio ,  Ferla, Giuseppe ,  Camalleri, Marco

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66712

Abstract: The invention relates to a vertical-conduction and planar-structure MOS device having a double thickness of gate oxide comprising

a first portion (5a) of gate oxide having a lower thickness in a channel area close to the active areas (4), and a second portion (5b) of thicker gate oxide in a central area (11) on a JFET area and
an enrichment region (9) in the JFET area under the second . portion (5b) of thicker gate oxide (11).

The invention also relates to a method for realising on a semiconductor substrate (2) MOS transistor electronic devices (1) with improved static and dynamic performances and high scaling down density, these transistors having traditional active areas (4) defined in the substrate (2) at the periphery of a channel region whereon a gate region is realised. The method provides at least the following steps:

realising the MOS transistor starting from a planar structure with a double thickness of gate oxide comprising a thin layer in the channel area close to the active areas (4) and a thicker layer in the central area (11) on the channel; and
realising an enrichment region (9) in the JFET area below the thicker layer.

Abstract translation: 本发明涉及一种垂直导电和平面结构MOS器件，其具有栅极氧化物的双重厚度，其包括在接近有源区（4）的沟道区中具有较低厚度的栅极氧化物的第一部分（5a） 在JFET区域上的中心区域（11）中较厚的栅极氧化物的第二部分（5b）和第二部分的JFET区域中的富集区域（9）。 较厚栅极氧化物（11）的部分（5b）。 本发明还涉及一种在具有改进的静态和动态性能以及高缩小密度的半导体衬底（2）MOS晶体管电子器件（1）上实现的方法，这些晶体管具有传统的有源区域（4） 在实现栅极区域的沟道区域的周围的衬底（2）。 该方法至少提供以下步骤：从具有双重厚度的栅极氧化物的平面结构开始实现MOS晶体管，该栅极氧化物在靠近有源区域（4）的沟道区域中具有薄层，并且在中心区域中具有较厚层（ 11）在频道上 并且在较厚层下面的JFET区域中实现富集区域（9）。

公开(公告)号：EP1113492A1

公开(公告)日：2001-07-04

申请号：EP99830826.6

申请日：1999-12-31

Applicant: STMicroelectronics S.r.l. ,  CNR-IMETEM

Inventor： D'Arrigo, Giuseppe ,  Spinella, Corrado ,  Coffa, Salvatore ,  Arena, Giuseppe ,  Camalleri, Marco

IPC: H01L21/762 ,  H01L21/316

CPC classification number: H01L21/3063 ,  C25F3/12 ,  H01L21/31662 ,  H01L21/32105 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76286

Abstract: This invention relates to a method of fabricating a SOI (Silicon-On-Insulator) wafer suitable to manufacture electronic semiconductor devices and including a substrate of monocrystalline silicon with a top surface, and a doped buried region in the substrate. The method comprises at least one step of forming trench-like openings extended from the substrate surface down to the buried region, and comprises:

a selective etching step carried out through said openings to change said buried region of monocrystalline silicon into porous silicon;
a subsequent step of oxidising the buried region that has been changed into porous silicon, to obtain an insulating portion of said SOI wafer.

Abstract translation: 本发明涉及一种制造适合于制造电子半导体器件并包括具有顶表面的单晶硅衬底以及衬底中的掺杂掩埋区的SOI（绝缘体上硅）晶片的方法。 该方法包括形成从衬底表面向下延伸到掩埋区域的沟槽状开口的至少一个步骤，并且包括：通过所述开口执行的选择性蚀刻步骤，以将所述单晶硅的掩埋区域改变为多孔硅; 氧化已经变成多孔硅的掩埋区域的后续步骤，以获得所述SOI晶片的绝缘部分。