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    Test structure for the measurement of contact to gate distance in non-volatile memory devices and corresponding test method
    2.
    发明公开
    Test structure for the measurement of contact to gate distance in non-volatile memory devices and corresponding test method 有权
    用于测量在非易失性存储器的非接触式门距离测试结构和相关联的测试程序

    公开(公告)号：EP1367597A1

    公开(公告)日：2003-12-03

    申请号：EP02425360.1

    申请日：2002-05-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Camerlenghi, Emilio ,  Cappelletti, Paolo ,  Ghilardi, Tecla ,  Sali, Mauro ,  Servalli, Giorgio

    IPC: G11C29/00

    CPC classification number: G11C29/006 ,  G11C16/04 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5002

    Abstract: The present invention relates to an improved integrated non-volatile memory device including a matrix of cells organised into rows, or word lines, and columns, or bit lines, and including corresponding row and column decoding circuits as well as read, modify and erase circuits for reading and modifying data stored in the memory cells. Advantageously, the integrated memory device comprises test structure (2) including a smaller second matrix (3) of cells comprising couples of word lines (WL) each having a difference contact to gate distance.
    Each couple of word lines is gradually misaligned from each adjacent couple of word lines by a distance that is variable from couple to couple.
    This proposed structure allows monitoring with a large statistic one of the most critical technology parameter for FLASH reliability.

    Abstract translation: 本发明涉及改进的集成的非易失性存储器装置，其包括组织为行的细胞，或字线，和列，或位线，的一个矩阵和包括对应的行和列解码电路以及读，修改和擦除电路 用于读取和修改存储在所述存储器单元中的数据。 有利地，所述集成的存储器装置包括测试结构（2）包括包含细胞的字线（WL）每一个都具有差接触到栅极距离耦合的较小的第二矩阵（3）。 每一对字线被从每个相邻的一对字线的距离逐渐错开确实是从耦合到耦合变量。 此提议的结构允许具有大统计量技术FLASH可靠性的最关键参数之一的监测。

    Single cell erasing method for recovering cells under programming disturbs in non volatile semiconductor memory devices
    4.
    发明公开
    Single cell erasing method for recovering cells under programming disturbs in non volatile semiconductor memory devices 有权
    EinzelzelllöschverfahrenderRückgewinnungvonprogammiergestörteZellen innichtflüchtigeSpeichervorrichtung

    公开(公告)号：EP1424700A1

    公开(公告)日：2004-06-02

    申请号：EP02425727.1

    申请日：2002-11-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Camerlenghi, Emilio ,  Campardo, Giovanni ,  Ghilardi, Tecla

    IPC: G11C16/34

    CPC classification number: G11C16/3431 ,  G11C16/3404 ,  G11C16/3418

    Abstract: The present invention relates to a particular single cell erasing method for recovering memory cells under reading or programming disturbs in non volatile semiconductor memory electronic devices comprising cell matrix split in sectors and organised in rows, or word lines, and columns, or bit lines.
    This kind of memory devices generally provides the application of a sector erasing algorithm with subsequent testing phase (erase-verify); but the method according to the present invention provides a bit by bit erasing by applying to each single word line a negative voltage used during the erasing of a whole sector and on the drain terminal of each single cell a programming voltage.
    With this kind of selective bias it is possible to perform a single cell, or bit by bit, erasing, allowing all the cells in case under a reading or programming disturb increasing the original threshold value thereof to be recovered.

    Abstract translation: 本发明涉及一种用于在非易失性半导体存储器电子设备中读取或编程干扰下的存储器单元的特定单元擦除方法，所述非易失性半导体存储器电子器件包括扇区中的单元矩阵分割并且以行或字线，列或位线组织。 这种存储器件通常提供具有随后的测试阶段（擦除验证）的扇区擦除算法的应用; 但是根据本发明的方法通过在每个单个字线上施加在擦除整个扇区期间使用的负电压并且在每个单个电池的漏极端子上施加编程电压来逐位擦除。 利用这种选择性偏置，可以执行单个单元或逐位擦除，从而允许在读取或编程干扰的情况下的所有单元增加其要恢复的原始阈值。

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