公开(公告)号：EP1249842B1

公开(公告)日：2009-08-26

申请号：EP01830247.1

申请日：2001-04-10

Applicant: STMicroelectronics S.r.l.

Inventor： Gregori, Stefano ,  Micheloni, Rino ,  Pierin, Andrea ,  Khouri, Osama ,  Torelli, Guido

IPC: G11C16/12

CPC classification number: G11C11/5628 ,  G11C16/12

公开(公告)号：EP1249842A1

公开(公告)日：2002-10-16

申请号：EP01830247.1

申请日：2001-04-10

Applicant: STMicroelectronics S.r.l.

Inventor： Gregori, Stefano ,  Micheloni, Rino ,  Pierin, Andrea ,  Khouri, Osama ,  Torelli, Guido

IPC: G11C16/12

CPC classification number: G11C11/5628 ,  G11C16/12

Abstract: Described herein is a method for programming a nonvolatile memory cell (1), which envisages applying in succession, to the gate terminal (2) of the memory cell (1), at least a first and a second programming pulse trains (F1, F2) with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next in the first programming pulse train (F1) is greater than the amplitude increment between one pulse and the next in the second programming pulse train (F2). Advantageously, the programming method envisages applying, to the gate terminal (2) of the memory cell (1) and before the first programming pulse train (F1), also a third programming pulse train (F0; F3) with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next may be less than the amplitude increment in the first programming pulse train (F1) and substantially equal to the amplitude increment in the second programming pulse train (F2), or else may be greater than the amplitude increment in the first programming pulse train (F1).

Abstract translation: 该方法涉及将相继地向存储单元的控制端子，至少两个编程脉冲串（F1，F2）与脉冲幅度在楼梯方式增加。 一个脉冲，并在第一编程脉冲串（F1）的下一个之间的幅度增量比一个脉冲，并在第二编程脉冲串（F2）的下一个之间的幅度增量越大。 从所述第一编程脉冲来训练到第二转换时当存储器单元具有与一个参考值的预先设定的关系的阈值电压。

公开(公告)号：EP1211812A2

公开(公告)日：2002-06-05

申请号：EP00127649.2

申请日：2000-11-23

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Khouri, Osama ,  Pierin, Andrea ,  Gregori, Stefano ,  Torelli, Guido

IPC: H03M1/14

CPC classification number: G11C11/56 ,  G11C27/005 ,  H03M1/146 ,  H03M1/361

Abstract: The invention relates to an analog-to-digital conversion method and relevant device, in high-density multilevel non-volatile memory devices. The method applies to multilevel memory cells comprising a floating gate transistor with drain and source terminals; the cell to be read is subjected to a reading operation by applying predetermined bias voltage values to its drain and source terminals, while to its drain terminal is applied a predetermined current value (Iref), and by measuring the value of its gate voltage (Vg).
The method of the invention comprises a first conversion phase the most significant bits (MSB) contained in the memory cell, followed by a second conversion phase of the least significant bits (LSB).
The first step is completed within a time gap (T1-T0) which corresponds to the rise transient of the gate voltage signal (Vg), while the second step is started at the end of the transient.

Abstract translation: 本发明涉及到模拟 - 数字转换方法和相关的设备，在高密度的多级非易失性存储器装置。 该方法适用于多级存储器单元包括具有漏极和源极端子的浮栅晶体管; 要读出的单元是通过，施加预定的偏置电压值到它的漏极和源极端，而其漏极端子施加规定的电流值（Iref的）经受读取操作，并通过测量其栅极电压的值（Vg的 ）。 本发明的方法包括包含在所述存储器单元中的最显著位（MSB）的第一转化阶段，接着是至少显著位的第二阶段的转换（LSB）。 第一个步骤是一个时间间隙（T1-T0），其对应于栅极电压信号（VG）的上升瞬变内完成，而第二个步骤是在瞬变结束启动。

公开(公告)号：EP1211812B1

公开(公告)日：2006-11-15

申请号：EP00127649.2

申请日：2000-11-23

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Khouri, Osama ,  Pierin, Andrea ,  Gregori, Stefano ,  Torelli, Guido

IPC: H03M1/14 ,  G11C11/56

CPC classification number: G11C11/56 ,  G11C27/005 ,  H03M1/146 ,  H03M1/361

公开(公告)号：EP1211812A3

公开(公告)日：2003-02-12

申请号：EP00127649.2

申请日：2000-11-23

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Khouri, Osama ,  Pierin, Andrea ,  Gregori, Stefano ,  Torelli, Guido

IPC: H03M1/14 ,  G11C11/56

CPC classification number: G11C11/56 ,  G11C27/005 ,  H03M1/146 ,  H03M1/361

Abstract: The invention relates to an analog-to-digital conversion method and relevant device, in high-density multilevel non-volatile memory devices. The method applies to multilevel memory cells comprising a floating gate transistor with drain and source terminals; the cell to be read is subjected to a reading operation by applying predetermined bias voltage values to its drain and source terminals, while to its drain terminal is applied a predetermined current value (Iref), and by measuring the value of its gate voltage (Vg). The method of the invention comprises a first conversion phase the most significant bits (MSB) contained in the memory cell, followed by a second conversion phase of the least significant bits (LSB). The first step is completed within a time gap (T1-T0) which corresponds to the rise transient of the gate voltage signal (Vg), while the second step is started at the end of the transient.