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    Voltage regulating circuit for a capacitive load
    4.
    发明公开
    Voltage regulating circuit for a capacitive load 有权
    Spannungsreglerfüreine kapazitive最后

    公开(公告)号：EP1065580A1

    公开(公告)日：2001-01-03

    申请号：EP99830418.2

    申请日：1999-06-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Khouri, Osama ,  Micheloni, Rino ,  Motta, Ilaria ,  Torelli, Guido

    IPC: G05F3/02 ,  G05F1/56 ,  G05F3/26 ,  H02J7/16

    CPC classification number: G05F3/242

    Abstract: A voltage regulating circuit for a capacitive load, being connected between first and second terminals of a supply voltage generator (VDD,GND) and having an input terminal (IN) and an output terminal (OUT), comprises an operational amplifier (OP) having an inverting (-) input terminal connected to the input terminal (IN) of the regulating circuit and a non-inverting (+) input terminal connected to an intermediate node of a voltage divider (R1,R2) which is connected between an output node connected to the output terminal (OUT) of the regulating circuit and the second terminal (GND) of the supply voltage generator, and having an output terminal connected, for driving a first field-effect transistor (MPU), between the output node and the first terminal (VDD) of the supply voltage generator, the output terminal of the operational amplifier being further connected to the output node through a compensation network (COMP), and comprises a second field-effect transistor (MPD1) connected between the output node and the second terminal of the supply voltage generator (GND) and having its gate terminal connected to a constant voltage generating circuit means (RB,CB,MB,IB).

    Abstract translation: 一种用于电容性负载的电压调节电路，连接在电源电压发生器（VDD，GND）的第一和第二端子之间并具有输入端（IN）和输出端（OUT），包括运算放大器（OP），其具有 连接到调节电路的输入端子（IN）的反相（ - ）输入端子和连接到分压器（R1，R2）的中间节点的非反相（+）输入端子，其连接在输出节点 连接到调节电路的输出端子（OUT）和电源电压发生器的第二端子（GND），并且具有用于驱动第一场效应晶体管（MPU）的输出端子连接在输出节点和 电源电压发生器的第一端子（VDD），运算放大器的输出端子通过补偿网络（COMP）进一步连接到输出节点，并且包括一个与之相连的第二场效应晶体管（MPD1） 在电源电压发生器（GND）的输出节点和第二端子上，并且其栅极端子连接到恒定电压发生电路装置（RB，CB，MB，IB）。

    Phase change memory device with overvoltage protection and method for protecting a phase change memory device against overvoltages
    9.
    发明公开
    Phase change memory device with overvoltage protection and method for protecting a phase change memory device against overvoltages 有权
    相变存储器以浪涌保护和保护方法，用于相变存储器与浪涌保护

    公开(公告)号：EP1538632A1

    公开(公告)日：2005-06-08

    申请号：EP03425728.7

    申请日：2003-11-12

    Applicant: STMicroelectronics S.r.l. ,  Universita' Degli Studi Di Pavia

    Inventor： Bedeschi, Ferdinando ,  Resta, Claudio ,  Torelli, Guido

    IPC: G11C11/34 ,  G11C7/12

    CPC classification number: G11C13/0004 ,  G11C7/12 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0059 ,  G11C2013/0054 ,  G11C2213/79

    Abstract: A phase change memory device includes a plurality of PCM cells (3), arranged in rows and columns, PCM cells (3) arranged on the same column being connected to a same bit line (10); a plurality of first selectors (12), each coupled to a respective PCM cell (3); an addressing circuit (4, 5) for selectively addressing at least one of the bit lines (10), one of the first selectors (12), and the PCM cell (3) connected to the addressed bit line (10) and to the addressed first selector (12); and a regulated voltage supply circuit (7, 14, 15), selectively connectable to the addressed bit line (10), for supplying a bit line voltage (V BL ). The bit line voltage (V BL ) is correlated to a first control voltage (V EBA ) on the addressed first selector (12), coupled to the addressed PCM cell (3).

    Abstract translation: 一种相变存储器装置包括PCM单元的多个（3），以行和列布置，PCM单元（3）布置在相同的列被连接到相同的位线（10）; 第一选择器的多个（12），每个耦合到respectivement PCM单元（3）; 在用于选择性地寻址所述位线中的至少一个（10）中，第一选择器中的一个（12）和所述PCM单元寻址电路（4,5）（3）连接到所寻址的位线（10）和所述 寻址第一选择器（12）; 和经调节的电压供给电路（7，14，15）选择性地连接到用于供给位线电压（VBL）被寻址的位线（10）。 位线电压（VBL）被关联以在被寻址第一选择器（12），耦合到所寻址的PCM单元（3）的第一控制电压（VEBA）。

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