Abstract:
The invention relates to a driving circuit for row decoding which is also useful in non-volatile memory devices of the multi-level Flash type and allows the overall capacitive load, as seen from the program voltage generator and the read/verify voltage generator, to be drastically reduced without involving segmentation of the decoding.
Abstract:
Described herein is a method for programming a nonvolatile memory cell (1), which envisages applying in succession, to the gate terminal (2) of the memory cell (1), at least a first and a second programming pulse trains (F1, F2) with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next in the first programming pulse train (F1) is greater than the amplitude increment between one pulse and the next in the second programming pulse train (F2). Advantageously, the programming method envisages applying, to the gate terminal (2) of the memory cell (1) and before the first programming pulse train (F1), also a third programming pulse train (F0; F3) with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next may be less than the amplitude increment in the first programming pulse train (F1) and substantially equal to the amplitude increment in the second programming pulse train (F2), or else may be greater than the amplitude increment in the first programming pulse train (F1).
Abstract:
A selector switch monolithically integrated to a CMOS technology circuit for electrically programmable memory cell devices having at least first and second input terminals for coupling to first and second voltage generators (HV and LV), respectively, and an output terminal (OUT). First (P1) and second (P2) field-effect selection transistors are respectively connected, via first and second terminals, between the first input terminal and the output terminal and between the second input terminal and the output terminal. These transistors are driven through control terminals at non-overlapping phases and have body terminals connected at a body circuit node (BODY) which is coupled to the first and second voltage generators through a bias circuit block (WBC) effective to bias the node to the higher of the instant voltages generated by the first and second generators.
Abstract:
A charge pump circuit, connected between a first voltage reference and an output terminal, comprises at least two stages consisting of an elementary charge pump circuit connected between said first voltage reference and said output terminal, and adjustment circuitry connected between said output terminal and respective control terminals of said at least two stages. This circuitry is arranged to select for actuation an appropriate combination of these elementary stages according to the current absorbed from a load connected to the output terminal.
Abstract:
The invention relates to an analog-to-digital conversion method and relevant device, in high-density multilevel non-volatile memory devices. The method applies to multilevel memory cells comprising a floating gate transistor with drain and source terminals; the cell to be read is subjected to a reading operation by applying predetermined bias voltage values to its drain and source terminals, while to its drain terminal is applied a predetermined current value (Iref), and by measuring the value of its gate voltage (Vg). The method of the invention comprises a first conversion phase the most significant bits (MSB) contained in the memory cell, followed by a second conversion phase of the least significant bits (LSB). The first step is completed within a time gap (T1-T0) which corresponds to the rise transient of the gate voltage signal (Vg), while the second step is started at the end of the transient.
Abstract:
This invention relates to a non-volatile memory device (20) with configurable row redundancy, comprising:
a non-volatile memory (11) comprising of at least one matrix (11') of memory cells and at least one matrix (11") of redundant memory cells, both organised into rows and columns; row and column decoding circuits (12,13); read and modify circuits for reading and modifying data stored in the memory cells; and at least one associative memory matrix (14), also organised into rows and columns, able to store the addresses of faulty rows, and control circuits for controlling the associative memory matrix.
The memory device (20) of this invention further comprises:
at least one circuit for recognising and comparing selected row addresses (ADr) with faulty row addresses (ADrr) contained in the associative memory matrix (14), such as to produce de-selection of the faulty row and selection of the corresponding redundant cell row in the event of a valid recognition; and at least one configuration register (17), also comprising a matrix of non-volatile memory cells, and associated control circuits.