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    Method for programming nonvolatile memory cells with program and verify algorithm using a staircase voltage with varying step amplitude
    4.
    发明公开
    Method for programming nonvolatile memory cells with program and verify algorithm using a staircase voltage with varying step amplitude 有权
    一种用于使用阶梯状的电压脉冲与步骤之间的可变距离编程非易失性存储器单元以编程和测试算法方法

    公开(公告)号：EP1249842A1

    公开(公告)日：2002-10-16

    申请号：EP01830247.1

    申请日：2001-04-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Gregori, Stefano ,  Micheloni, Rino ,  Pierin, Andrea ,  Khouri, Osama ,  Torelli, Guido

    IPC: G11C16/12

    CPC classification number: G11C11/5628 ,  G11C16/12

    Abstract: Described herein is a method for programming a nonvolatile memory cell (1), which envisages applying in succession, to the gate terminal (2) of the memory cell (1), at least a first and a second programming pulse trains (F1, F2) with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next in the first programming pulse train (F1) is greater than the amplitude increment between one pulse and the next in the second programming pulse train (F2). Advantageously, the programming method envisages applying, to the gate terminal (2) of the memory cell (1) and before the first programming pulse train (F1), also a third programming pulse train (F0; F3) with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next may be less than the amplitude increment in the first programming pulse train (F1) and substantially equal to the amplitude increment in the second programming pulse train (F2), or else may be greater than the amplitude increment in the first programming pulse train (F1).

    Abstract translation: 该方法涉及将相继地向存储单元的控制端子，至少两个编程脉冲串（F1，F2）与脉冲幅度在楼梯方式增加。 一个脉冲，并在第一编程脉冲串（F1）的下一个之间的幅度增量比一个脉冲，并在第二编程脉冲串（F2）的下一个之间的幅度增量越大。 从所述第一编程脉冲来训练到第二转换时当存储器单元具有与一个参考值的预先设定的关系的阈值电压。

    Monolithically integrated selector for electrically programmable memory cells devices
    5.
    发明公开
    Monolithically integrated selector for electrically programmable memory cells devices 失效
    Monolithisch integrierter Umschalterfürelektrisch programmierbare Speicherzellenvorrichtungen

    公开(公告)号：EP0961288A1

    公开(公告)日：1999-12-01

    申请号：EP98830332.7

    申请日：1998-05-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Manstretta, Alessandro ,  Pierin, Andrea ,  Torelli, Guido

    IPC: G11C16/06

    CPC classification number: G11C16/12

    Abstract: A selector switch monolithically integrated to a CMOS technology circuit for electrically programmable memory cell devices having at least first and second input terminals for coupling to first and second voltage generators (HV and LV), respectively, and an output terminal (OUT).
    First (P1) and second (P2) field-effect selection transistors are respectively connected, via first and second terminals, between the first input terminal and the output terminal and between the second input terminal and the output terminal. These transistors are driven through control terminals at non-overlapping phases and have body terminals connected at a body circuit node (BODY) which is coupled to the first and second voltage generators through a bias circuit block (WBC) effective to bias the node to the higher of the instant voltages generated by the first and second generators.

    Abstract translation: 选择器开关单片集成到用于电可编程存储器单元器件的CMOS工艺电路，其具有至少分别用于耦合到第一和第二电压发生器（HV和LV）的第一和第二输入端子以及输出端子（OUT）。 第一（P1）和第二（P2）场效应选择晶体管分别经由第一和第二端子在第一输入端和输出端之间以及第二输入端和输出端之间连接。 这些晶体管以不重叠的相位被驱动通过控制端子，并且具有连接在体电路节点（BODY）的主体端子，其通过偏置电路块（WBC）耦合到第一和第二电压发生器，该偏置电路块有效地将节点偏置到 由第一和第二发生器产生的瞬时电压越高。

    Low power charge pump circuit
    6.
    发明公开
    Low power charge pump circuit 有权
    Leungung Ladungspumpeschaltung mit niedriger

    公开(公告)号：EP1310959A1

    公开(公告)日：2003-05-14

    申请号：EP01830695.1

    申请日：2001-11-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Khouri, Osama ,  Soltesz, Dario ,  Pierin, Andrea ,  Torrelli, Guido

    IPC: G11C5/14 ,  H02M3/07

    CPC classification number: G11C5/145 ,  H02M3/073 ,  H02M2001/0032 ,  H02M2003/075 ,  H02M2003/077 ,  Y02B70/16

    Abstract: A charge pump circuit, connected between a first voltage reference and an output terminal, comprises at least two stages consisting of an elementary charge pump circuit connected between said first voltage reference and said output terminal, and adjustment circuitry connected between said output terminal and respective control terminals of said at least two stages. This circuitry is arranged to select for actuation an appropriate combination of these elementary stages according to the current absorbed from a load connected to the output terminal.

    Abstract translation: 连接在第一参考电压和输出端子之间的电荷泵电路包括由连接在所述第一电压基准和所述输出端子之间的基本电荷泵电路和连接在所述输出端子和相应控制器之间的调节电路组成的至少两级 所述至少两个阶段的终端。 该电路被设置为根据从连接到输出端子的负载吸收的电流来选择这些基本级的适当组合。

    A/D conversion method in high density multilevel non-volatile memory devices and corresponding converter device
    7.
    发明公开
    A/D conversion method in high density multilevel non-volatile memory devices and corresponding converter device 有权
    在非易失性更通常高密度存储器和相关联的换能器为模拟/数字转换的方法

    公开(公告)号：EP1211812A2

    公开(公告)日：2002-06-05

    申请号：EP00127649.2

    申请日：2000-11-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Khouri, Osama ,  Pierin, Andrea ,  Gregori, Stefano ,  Torelli, Guido

    IPC: H03M1/14

    CPC classification number: G11C11/56 ,  G11C27/005 ,  H03M1/146 ,  H03M1/361

    Abstract: The invention relates to an analog-to-digital conversion method and relevant device, in high-density multilevel non-volatile memory devices. The method applies to multilevel memory cells comprising a floating gate transistor with drain and source terminals; the cell to be read is subjected to a reading operation by applying predetermined bias voltage values to its drain and source terminals, while to its drain terminal is applied a predetermined current value (Iref), and by measuring the value of its gate voltage (Vg).
    The method of the invention comprises a first conversion phase the most significant bits (MSB) contained in the memory cell, followed by a second conversion phase of the least significant bits (LSB).
    The first step is completed within a time gap (T1-T0) which corresponds to the rise transient of the gate voltage signal (Vg), while the second step is started at the end of the transient.

    Abstract translation: 本发明涉及到模拟 - 数字转换方法和相关的设备，在高密度的多级非易失性存储器装置。 该方法适用于多级存储器单元包括具有漏极和源极端子的浮栅晶体管; 要读出的单元是通过，施加预定的偏置电压值到它的漏极和源极端，而其漏极端子施加规定的电流值（Iref的）经受读取操作，并通过测量其栅极电压的值（Vg的 ）。 本发明的方法包括包含在所述存储器单元中的最显著位（MSB）的第一转化阶段，接着是至少显著位的第二阶段的转换（LSB）。 第一个步骤是一个时间间隙（T1-T0），其对应于栅极电压信号（VG）的上升瞬变内完成，而第二个步骤是在瞬变结束启动。

    Non-volatile memory device with configurable row redundancy
    8.
    发明公开
    Non-volatile memory device with configurable row redundancy 有权
    NichtflüchtigeSpeicheranordnung mit konfigurierbarer Zeilenredundanz

    公开(公告)号：EP1126372A1

    公开(公告)日：2001-08-22

    申请号：EP00830103.8

    申请日：2000-02-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Manstretta, Alessandro ,  Micheloni, Rino ,  Pierin, Andrea ,  Yero, Emilio

    IPC: G06F11/20

    CPC classification number: G11C29/70

    Abstract: This invention relates to a non-volatile memory device (20) with configurable row redundancy, comprising:

    a non-volatile memory (11) comprising of at least one matrix (11') of memory cells and at least one matrix (11") of redundant memory cells, both organised into rows and columns;
    row and column decoding circuits (12,13);
    read and modify circuits for reading and modifying data stored in the memory cells; and
    at least one associative memory matrix (14), also organised into rows and columns, able to store the addresses of faulty rows, and control circuits for controlling the associative memory matrix.

    The memory device (20) of this invention further comprises:

    at least one circuit for recognising and comparing selected row addresses (ADr) with faulty row addresses (ADrr) contained in the associative memory matrix (14), such as to produce de-selection of the faulty row and selection of the corresponding redundant cell row in the event of a valid recognition; and
    at least one configuration register (17), also comprising a matrix of non-volatile memory cells, and associated control circuits.

    Abstract translation: 本发明涉及一种具有可配置行冗余性的非易失性存储器件（20），包括：非易失性存储器（11），包括至少一个存储器单元矩阵（11'）和至少一个矩阵（11“）， 冗余存储器单元，被组织成行和列;行和列解码电路（12,13）;用于读取和修改存储在存储器单元中的数据的读取和修改电路;以及至少一个关联存储器矩阵（14） 本发明的存储器件（20）还包括：用于识别和比较所选行地址（ADr）的至少一个电路 ），包括在所述关联存储器矩阵（14）中的有缺陷的行地址（ADrr），以便在有效识别的情况下产生故障行的选择和对应的冗余单元行的选择;以及至少一个配置 （17），还包括非易失性存储器单元矩阵和相关联的控制电路。

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