Abstract:
A process for the fabrication of integrated resistive elements with protection from silicidation envisages the steps of: delimiting, in a semiconductor wafer (10), at least one active area (15); and forming, in the active area (15) at least one resistive region (21) having a pre-determined resistivity. Prior to forming the resistive region (21), on top of the active area (15) a delimitation structure (20) for delimiting the resistive region (21) is obtained, and, subsequently, protective elements (25), which extend within the delimitation structure (20) and coat the resistive region (21), are obtained.
Abstract:
The process for the manufacturing electronic devices including memory cells (72) comprises the steps of: forming, on a substrate (2) of semiconductor material, multilayer stacks (54) including a floating gate region (40a), an intermediate dielectric region (41a), and a control gate region (50a); forming a protective layer (75) extending on top of the substrate (2) and between the multilayer stacks (54) and having a height at least equal to the multilayer stacks. The step of forming multilayer stacks (54) comprises the step of defining the control gate region (50a) on all sides so that each control gate region is completely separate from adjacent control gate regions. The protective layer (75) isolates the multilayer stacks (54) from each other at the sides. Word lines (80a) of metal extend above the protective layer (75) and are in electrical contact with the gate regions.