公开(公告)号：EP1403909A1

公开(公告)日：2004-03-31

申请号：EP02425586.1

申请日：2002-09-30

Applicant: STMicroelectronics S.r.l.

Inventor： Grossi, Alessandro ,  Bez, Roberto ,  Servalli, Giorgio

IPC: H01L21/02 ,  H01L27/08

CPC classification number: H01L28/20 ,  H01L27/0802

Abstract: A process for the fabrication of integrated resistive elements with protection from silicidation envisages the steps of: delimiting, in a semiconductor wafer (10), at least one active area (15); and forming, in the active area (15) at least one resistive region (21) having a pre-determined resistivity. Prior to forming the resistive region (21), on top of the active area (15) a delimitation structure (20) for delimiting the resistive region (21) is obtained, and, subsequently, protective elements (25), which extend within the delimitation structure (20) and coat the resistive region (21), are obtained.

Abstract translation: 集成电阻器通过在半导体晶片（10）中限定至少一个有效区域来制造; 以及在所述有源区域中形成具有预设电阻率的电阻区域。 在有源区域的顶部，形成用于限定电阻区域的定界结构。 获得了在限定结构内延伸并覆盖电阻区域的保护元件。

公开(公告)号：EP1104023A1

公开(公告)日：2001-05-30

申请号：EP99830735.9

申请日：1999-11-26

Applicant: STMicroelectronics S.r.l.

Inventor： Grossi, Alessandro ,  Clementi, Cesare

IPC: H01L21/8247 ,  H01L21/8239 ,  H01L27/115

CPC classification number: H01L27/11526 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11536

Abstract: The process for the manufacturing electronic devices including memory cells (72) comprises the steps of: forming, on a substrate (2) of semiconductor material, multilayer stacks (54) including a floating gate region (40a), an intermediate dielectric region (41a), and a control gate region (50a); forming a protective layer (75) extending on top of the substrate (2) and between the multilayer stacks (54) and having a height at least equal to the multilayer stacks. The step of forming multilayer stacks (54) comprises the step of defining the control gate region (50a) on all sides so that each control gate region is completely separate from adjacent control gate regions. The protective layer (75) isolates the multilayer stacks (54) from each other at the sides. Word lines (80a) of metal extend above the protective layer (75) and are in electrical contact with the gate regions.

Abstract translation: 包括存储单元（72）的制造电子器件的方法包括以下步骤：在半导体材料的衬底（2）上形成包括浮动栅极区（40a），中间介电区（41a）的多层堆叠（54） ）和控制栅极区（50a）; 形成在衬底（2）的顶部和多层堆叠（54）之间延伸并具有至少等于多层堆叠的高度的保护层（75）。 形成多层堆叠（54）的步骤包括在所有侧面上限定控制栅极区域（50a）的步骤，使得每个控制栅极区域与相邻的控制栅极区域完全分离。 保护层（75）将多层堆叠（54）在侧面彼此隔离。 金属字线（80a）在保护层（75）上方延伸并与栅极区域电接触。