公开(公告)号：EP0591599B1

公开(公告)日：2001-12-19

申请号：EP92830542.4

申请日：1992-09-30

Applicant: STMicroelectronics S.r.l.

Inventor： Crisenza, Giuseppe ,  Clementi, Cesare

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L27/11526 ,  H01L21/823842 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/11546

公开(公告)号：EP0591598B1

公开(公告)日：1998-12-02

申请号：EP92830541.6

申请日：1992-09-30

Applicant: STMicroelectronics S.r.l.

Inventor： Crisenza, Giuseppe ,  Clementi, Cesare

IPC: H01L21/28 ,  H01L29/41

CPC classification number: H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825

公开(公告)号：EP1435647A1

公开(公告)日：2004-07-07

申请号：EP02425806.3

申请日：2002-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Baldi, Livio ,  Clementi, Cesare ,  Pavan, Alessia

IPC: H01L21/331 ,  H01L21/60

CPC classification number: H01L29/66272

Abstract: A method for forming structures self-aligned with each other on a semiconductor substrate (1), comprising the following steps:

forming, on the semiconductor substrate (1), first regions (3,12) of a first material projecting from the semiconductor substrate (1);
forming, over the whole of the semiconductor substrate (1), a protective layer (7,16) of a second material selective with respect to the first material;
removing the protective layer (7,16) to expose said first regions (3,12) through a planarizing step;
etching said first regions (3,12) to expose said semiconductor substrate (1), and forming second regions (7a,16a) projecting from the substrate (1) of said protective layer.

Advantageously, spacers are formed on the sidewalls of the first regions.

Abstract translation: 一种形成在半导体衬底（1）上彼此自对准的结构的方法，包括以下步骤：在半导体衬底（1）上形成从半导体衬底（1）突出的第一材料的第一区域（3,12） （1）; 在整个半导体衬底（1）上形成相对于第一材料选择性的第二材料的保护层（7,16）; 去除所述保护层（7,16）以通过平坦化步骤暴露所述第一区域（3,12）; 蚀刻所述第一区域（3,12）以暴露所述半导体衬底（1），以及形成从所述保护层的衬底（1）突出的第二区域（7a，16a）。 有利地，间隔物形成在第一区域的侧壁上。

公开(公告)号：EP1435657A1

公开(公告)日：2004-07-07

申请号：EP02425805.5

申请日：2002-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Pavan, Alessia ,  Clementi, Cesare ,  Baldi, Livio

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A non-volatile memory cell (1) is described, being integrated on a semiconductor substrate (2) and comprising:

a floating gate transistor including a source region (S) and a drain region (G), a gate region projecting from the substrate (2) and comprised between the source and drain regions (S, D), the gate region having a predetermined length (L) and width (W) and comprising a first floating gate region (FG) and a control gate region (CG),
in which the floating gate region (FG) is insulated laterally, along the width (W) direction, by a dielectric layer (9) with low dielectric constant value (K).
A process for manufacturing non-volatile memory cells (1) on a semiconductor substrate (2) is also described, comprising the following steps:

form active areas in the semiconductor substrate (2) bounded by an insulating layer (FOX),
deposit a first conductor material layer (5) on active areas,
define through a standard photolithographic technique a plurality of floating gate regions (FG),
form a dielectric layer (9) with low dielectric constant value (K) on the floating gate regions (FG).

Abstract translation: 描述了集成在半导体衬底（2）上的非易失性存储器单元（1），包括：包括源区（S）和漏区（G）的浮栅晶体管，从衬底 （2）并且包括在源极和漏极区域（S，D）之间，栅极区域具有预定长度（L）和宽度（W），并且包括第一浮动栅极区域（FG）和控制栅极区域（CG） ，其中浮动栅极区域（FG）沿着宽度（W）方向由具有低介电常数值（K）的电介质层（9）侧向绝缘。 还描述了一种用于在半导体衬底（2）上制造非易失性存储单元（1）的工艺，包括以下步骤：在由绝缘层（FOX）限定的半导体衬底（2）中形成有源区， 在有源区域上沉积第一导体材料层（5），通过标准光刻技术限定多个浮动栅极区域（FG），在浮动栅极区域上形成具有低介电常数值（K）的介电层（9） （FG）。

公开(公告)号：EP1111673A1

公开(公告)日：2001-06-27

申请号：EP01200376.0

申请日：1995-05-10

Applicant: STMicroelectronics S.r.l.

Inventor： Ghidini, Gabriella ,  Clementi, Cesare

IPC: H01L21/8247 ,  H01L21/8239

CPC classification number: H01L27/11526 ,  H01L21/3145 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10844 ,  H01L27/11539

Abstract: The method described provides for the formation of thin thermal oxide on areas of a silicon die intended for memory cells and other components of the peripheral circuits of the memory. To obtain the best dielectrics both for the memory cells and for the components of the peripheral circuits the method comprises a step for high-temperature nitriding of the oxide, a step for removing the nitrided oxide from the areas intended for the components of the peripheral circuits and a step for forming again a nitrided thermal oxide on the exposed areas.

Abstract translation: 所述的方法提供了在用于存储器单元的硅芯片和存储器的外围电路的其它部件的区域上形成薄热氧化物。 为了提高电池氧化物的质量，基本上是由于在存储器的操作期间由于电荷通过它而导致的降解性的降低，该方法提供了氧化物的高温氮化的步骤。 根据一个变型，在用于外围电路的部件的区域上形成的氮化氧化物被除去，然后通过类似的热氧化处理再次形成，然后进行高温氮化。

公开(公告)号：EP1104023A1

公开(公告)日：2001-05-30

申请号：EP99830735.9

申请日：1999-11-26

Applicant: STMicroelectronics S.r.l.

Inventor： Grossi, Alessandro ,  Clementi, Cesare

IPC: H01L21/8247 ,  H01L21/8239 ,  H01L27/115

CPC classification number: H01L27/11526 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11536

Abstract: The process for the manufacturing electronic devices including memory cells (72) comprises the steps of: forming, on a substrate (2) of semiconductor material, multilayer stacks (54) including a floating gate region (40a), an intermediate dielectric region (41a), and a control gate region (50a); forming a protective layer (75) extending on top of the substrate (2) and between the multilayer stacks (54) and having a height at least equal to the multilayer stacks. The step of forming multilayer stacks (54) comprises the step of defining the control gate region (50a) on all sides so that each control gate region is completely separate from adjacent control gate regions. The protective layer (75) isolates the multilayer stacks (54) from each other at the sides. Word lines (80a) of metal extend above the protective layer (75) and are in electrical contact with the gate regions.

Abstract translation: 包括存储单元（72）的制造电子器件的方法包括以下步骤：在半导体材料的衬底（2）上形成包括浮动栅极区（40a），中间介电区（41a）的多层堆叠（54） ）和控制栅极区（50a）; 形成在衬底（2）的顶部和多层堆叠（54）之间延伸并具有至少等于多层堆叠的高度的保护层（75）。 形成多层堆叠（54）的步骤包括在所有侧面上限定控制栅极区域（50a）的步骤，使得每个控制栅极区域与相邻的控制栅极区域完全分离。 保护层（75）将多层堆叠（54）在侧面彼此隔离。 金属字线（80a）在保护层（75）上方延伸并与栅极区域电接触。

公开(公告)号：EP1403917A1

公开(公告)日：2004-03-31

申请号：EP02425581.2

申请日：2002-09-26

Applicant: STMicroelectronics S.r.l.

Inventor： Brazzelli, Daniela ,  Clementi, Cesare

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/76235

Abstract: A process for manufacturing semiconductor wafers incorporating differentiated insulating structures envisages the steps of: opening first trenches (8) in a substrate (2) of a semiconductor wafer (1), the trenches delimiting first conductive regions (9) and having a first depth; and opening second trenches (16), delimiting second conductive regions (17) and having a second depth. Furthermore, the step of opening second trenches (16) is preceded by the step of forming first insulating sidewalls (12), which surround the first trenches (8), and is followed by the step of forming second insulating sidewalls (19), which surround the second trenches (16) .

Abstract translation: 该工艺涉及在半导体晶片（1）的衬底（2）中打开沟槽（8），其中沟槽界定导电区域（9）。 绝缘侧壁（12）形成在沟槽（8）周围。 打开另一组沟槽（16）以限定导电区域（17），并且沟槽（16）被绝缘侧壁（19）包围，其中沟槽具有不同的深度。 对于包括绝缘结构的半导体晶片，还包括独立权利要求。

公开(公告)号：EP0751560B1

公开(公告)日：2002-11-27

申请号：EP95830282.0

申请日：1995-06-30

Applicant: STMicroelectronics S.r.l.

Inventor： Clementi, Cesare ,  Ghidini, Gabriella ,  Riva, Carlo

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: A process for forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells (1) including an intermediate dielectric multilayer comprising a lower silicon oxide layer (7), an intermediate silicon nitride layer (8) and an upper silicon oxide layer (10) and the simultaneous provision in zones peripheral to the memory cells of at least one first (2) and one second (3) transistor type having gate dielectric of a first and a second thickness respectively. After formation of the floating gate of the cells with a gate oxide layer (5) and a polycrystalline silicon layer (6) and the formation of the lower silicon oxide layer (7) and of the intermediate silicon nitride layer (8), the process in accordance with the present invention includes: removal of said layers from the zones peripheral (R2,R3) to the matrix; formation of a first silicon oxide layer (9) over the substrate in the areas (R2,R3) of both types of transistor (2,3); removal of the preceding layer (9) from areas (R3) assigned only to the transistors (3) of the second type; deposition of said upper silicon oxide layer (10) over the memory cells (1), over the first silicon oxide layer (9) in the areas (R2) of the transistors (2) of the first type and over the substrate (4) in the areas (R3) of the transistors of the second type; and formation of a second silicon oxide layer (11) in the areas (R2,R3) of both types of peripheral transistors (2,3).

公开(公告)号：EP0751559B1

公开(公告)日：2002-11-27

申请号：EP95830281.2

申请日：1995-06-30

Applicant: STMicroelectronics S.r.l.

Inventor： Clementi, Cesare ,  Ghidini, Gabriella ,  Riva, Carlo

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: A process for forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells (1) having an intermediate dielectric multilayer including at least a lower dielectric material layer (8) and an upper silicon oxide layer (9) and the simultaneous provision in zones peripheral to the matrix of at least one first transistor type (2) having gate dielectric of a first thickness. After formation of the floating gate with a gate oxide layer (4) and a polycrystalline silicon layer (5) and the formation of the lower dielectric material layer (8), the process in accordance with the present invention calls for: removal of said layers from the peripheral zones (R2) of the matrix; deposition of said upper silicon oxide layer (9) over the memory cells (1),and over the substrate (3) in the areas (R2) of the peripheral transistors (2); and formation of a first silicon oxide layer (10) at least in the areas (R2) of the peripheral transistors (2). To provide additionally a second transistor type having gate dielectric of a second thickness, indicatively thinner than said first thickness, successive steps are added in accordance with the present invention.

公开(公告)号：EP0878833A3

公开(公告)日：1999-02-17

申请号：EP98830235.2

申请日：1998-04-20

Applicant: STMicroelectronics S.r.l.

Inventor： Moroni, Maurizio ,  Clementi, Cesare

IPC: H01L21/285

CPC classification number: H01L29/6659 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66659

Abstract: Process for forming salicide on active areas of MOS transistors (10,11), each comprising a gate (2) and respective source and drain regions (5,12;7,13;5A,5B), the source and drain regions comprising each a first lightly doped sub-region (5;7;5A) adjacent the gate (2) and a second highly doped sub-region (12;13;5B) spaced apart from the gate (2), characterized in that the salicide is formed selectively at least over the second highly doped sub-regions (12;13;58) of the source and drain regions of the MOS transistors, and not over the first lightly doped sub-region (5;7;5A).