公开(公告)号：WO2006103247A1

公开(公告)日：2006-10-05

申请号：PCT/EP2006/061118

申请日：2006-03-28

Applicant: STMICROELECTRONICS S.R.L. ,  PRANDI, Luciano ,  LASALANDRA, Ernesto ,  UNGARETTI, Tommaso

Inventor： PRANDI, Luciano ,  LASALANDRA, Ernesto ,  UNGARETTI, Tommaso

IPC: H03H9/02

CPC classification number: H03H9/02409 ,  G01C19/5726 ,  G01P15/097 ,  G01P15/125 ,  G01P2015/0814 ,  H03H2009/02496

Abstract: A device for controlling the frequency of resonance of an oscillating micro-electromechanical system includes: a microstructure (2), having a first body (10) and a second body (11) , which is capacitively coupled to the first body (10) and elastically oscillatable with respect thereto at a calibratable frequency of resonance (ω R ) , a relative displacement (ΔY) between the second body (11) and the first body (10) being detectable from outside; and an amplifier (21) coupled to the microstructure (2) for detecting the relative displacement (ΔY) . DC decoupling elements (23) are arranged between the amplifier (21) and the microstructure (2).

Abstract translation: 用于控制振荡微机电系统的共振频率的装置包括：具有电容耦合到第一主体（10）的第一主体（10）和第二主体（11）的微结构（2）和 以可校准的共振频率弹性振荡，第二体（11）和第一体（10）之间的相对位移（ΔY）可从外部检测; 以及耦合到微结构（2）的用于检测相对位移（ΔY）的放大器（21）。 DC去耦元件（23）布置在放大器（21）和微结构（2）之间。

公开(公告)号：WO2007042336A3

公开(公告)日：2007-04-19

申请号：PCT/EP2006/064298

申请日：2006-07-14

Applicant: STMicroelectronics S.r.l. ,  COMBI, Chantal ,  VIGNA, Benedetto ,  ZIGLIOLI, Federico Giovanni ,  BALDO, Lorenzo ,  MAGUGLIANI, Manuela ,  LASALANDRA, Ernesto ,  RIVA, Caterina

Inventor： COMBI, Chantal ,  VIGNA, Benedetto ,  ZIGLIOLI, Federico Giovanni ,  BALDO, Lorenzo ,  MAGUGLIANI, Manuela ,  LASALANDRA, Ernesto ,  RIVA, Caterina

IPC: B81B7/02 ,  B81B7/00

Abstract: In a substrate-level assembly (22), a device substrate (20) of semiconductor material has a top face (20a) and houses a first integrated device (1; 16), in particular provided with a buried cavity (3), formed within the device substrate (20), and with a membrane (4), suspended over the buried cavity (3) in the proximity of the top face (20a). A capping substrate (21) is coupled to the device substrate (20) above the top face (20a) so as to cover the first integrated device (1; 16), in such a manner that a first empty space (25) is provided above the membrane (4). Electrical-contact elements (28a, 28b) electrically connect the integrated device (1; 16) with the outside of the substrate-level assembly (22). In one embodiment, the device substrate (20) integrates at least a further integrated device (1', 10) provided with a respective membrane (4'); and a further empty space (25'), fluidically isolated from the first empty space (25), is provided over the respective membrane (4') of the further integrated device (1', 10).

公开(公告)号：EP1945561A2

公开(公告)日：2008-07-23

申请号：EP06777802.7

申请日：2006-07-14

Applicant: STMicroelectronics S.r.l.

Inventor： COMBI, Chantal ,  VIGNA, Benedetto ,  ZIGLIOLI, Federico Giovanni ,  BALDO, Lorenzo ,  MAGUGLIANI, Manuela ,  LASALANDRA, Ernesto ,  RIVA, Caterina

IPC: B81B7/02

CPC classification number: B81B7/0061 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81C1/0023 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/1461 ,  H01L2924/3025 ,  H04R1/04 ,  H04R19/005 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A substrate-level assembly having a device substrate of semiconductor material with a top face and housing a first integrated device, including a buried cavity formed within the device substrate, and with a membrane suspended over the buried cavity in the proximity of the top face. A capping substrate is coupled to the device substrate above the top face so as to cover the first integrated device in such a manner that a first empty space is provided above the membrane. Electrical-contact elements electrically connect the integrated device with the outside of the substrate-level assembly. In one embodiment, the device substrate integrates at least a further integrated device provided with a respective membrane, and a further empty space, fluidly isolated from the first empty space, is provided over the respective membrane of the further integrated device.

Abstract translation: 具有A衬底级组件的半导体材料的器件衬底具有顶面和外壳的第一集成器件，包括器件衬底内形成的掩埋空腔，并用悬浮在在顶面的接近掩埋空腔的膜。 甲封盖衬底耦合到所述顶面之上的器件衬底，以便覆盖所述第一集成器件在寻求做的膜上方提供第一空白空间的方式。 电接触元件电连接与所述衬底级组件的外部集成器件。 在一个实施例中，器件衬底至少集成设置有respectivement膜的进一步集成器件，和另外的空的空间，从所述第一空的空间流体地隔离，则在进一步的集成器件的respectivement膜提供。