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    Low dissipation biCMOS ECL/CMOS interface
    1.
    发明公开
    Low dissipation biCMOS ECL/CMOS interface 审中-公开
    Bi CMOS CMOS ECL / CMOS Schnittstelle mit Niedrigem Verbrauch

    公开(公告)号：EP1006658A1

    公开(公告)日：2000-06-07

    申请号：EP98830727.8

    申请日：1998-12-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ottini, Daniele ,  Bruccoleri, Melchiorre ,  Marchese, Stefano ,  Bollati, Giacomino

    IPC: H03K19/0175

    CPC classification number: H03K19/017527

    Abstract: A BiCMOS ECL/CMOS interface circuit for converting a high frequency pseudo-ECL signal with a voltage swing in the order of few hundreds of millivolts into a CMOS signal with a voltage swing substantially equal to the supply voltage, comprising a differential input stage composed of a pair of NPN bipolar junction transistors (Q1, Q2) in a common emitter configuration, a bias current generator (IBIAS) functionally coupled between the common emitter node of said NPN transistors and ground and means driven by a respective transistor of said input pair (Q1, Q2) driving the control node of a respective output CMOS stage (M5-M7, M6-M8), is provided with first and second common-collector stages each constituted by an NPN bipolar junction transistor(Q3, Q4) and driven by a respective transistor of said pair of NPN transistors (Q1, Q2); and with a pair of identical PMOS transistors (M1, M2) with gates connected in common to a bias voltage (POL), each PMOS transistor (M1, M2) having a source coupled to the emitter of a respective transistor (Q3, Q4) of said common-collector stages and a drain connected to a load current generator (I) and to said control node of a respective output CMOS stage (M5-M7, M6-M8), for reducing current absorption without impairing performance.

    Abstract translation: 一种BiCMOS ECL / CMOS接口电路，用于将具有几百毫伏数量级的电压摆幅的高频伪ECL信号转换成具有基本上等于电源电压的电压摆幅的CMOS信号，包括差分输入级，其由 一个共同的发射结构的一对NPN双极结晶体管（Q1，Q2），功能上耦合在所述NPN晶体管的公共发射极节点与地之间的偏置电流发生器（IBIAS）和由所述输入对的相应晶体管驱动的装置 Q1，Q2）驱动各个输出CMOS级（M5-M7，M6-M8）的控制节点，设置有由NPN双极结型晶体管（Q3，Q4）构成的第一和第二公共集电极级，并由 所述一对NPN晶体管（Q1，Q2）的相应晶体管; 并且通过一对具有与偏置电压（POL）共同连接的栅极的一对相同的PMOS晶体管（M1，M2），每个PMOS晶体管（M1，M2）具有耦合到相应晶体管（Q3，Q4）的发射极的源极， 的所述共集电极级和连接到负载电流发生器（I）的漏极以及相应的输出CMOS级（M5-M7，M6-M8）的所述控制节点，用于减小电流吸收而不损害性能。

    MOS transconductor with broad trimming range
    3.
    发明公开
    MOS transconductor with broad trimming range 审中-公开
    MOS跨导体具有宽广的修整范围

    公开(公告)号：EP1020990A3

    公开(公告)日：2000-08-02

    申请号：EP99830379.6

    申请日：1999-07-17

    Applicant: STMicroelectronics S.r.l.

    Inventor： Marchese, Stefano ,  Bollati, Giacomino ,  Malfa, Maurizio ,  Savo, Pierandrea

    IPC: H03F3/45

    CPC classification number: H03F3/45632 ,  H03F3/45197 ,  H03F2203/45466

    Abstract: A transconductor comprising a differential stage composed of a pair of input transistors, a resistive line of degeneration convecting the sources of the input transistors of said differential stage, a pair of bias current generators, each coupled between the source of a respective input transistor and a common ground node, has said resistive line of degeneration composed of one or more transistors in series, the gate of which is coupled to a voltage at least equal to the common mode voltage of the differential stage, and which are sized to operate in the triode region.

    Abstract translation: 一种跨导器，包括由一对输入晶体管构成的差分级，一个对所述差分级的输入晶体管的源极进行对流的负反馈电阻线，一对偏置电流发生器，每个偏置电流发生器耦合在相应输入晶体管的源极和 共同的接地节点具有由串联的一个或多个晶体管构成的电阻性退化线，其栅极耦合到至少等于差分级的共模电压的电压，并且其尺寸被设定为在三极管 地区。

    MOS transconductor with broad trimming range
    6.
    发明公开
    MOS transconductor with broad trimming range 审中-公开
    马克思主义者：Trimmungsbereich

    公开(公告)号：EP1020990A2

    公开(公告)日：2000-07-19

    申请号：EP99830379.6

    申请日：1999-07-17

    Applicant: STMicroelectronics S.r.l.

    Inventor： Marchese, Stefano ,  Bollati, Giacomino ,  Malfa, Maurizio ,  Savo, Pierandrea

    IPC: H03F3/45

    CPC classification number: H03F3/45632 ,  H03F3/45197 ,  H03F2203/45466

    Abstract: A transconductor comprising a differential stage composed of a pair of input transistors, a resistive line of degeneration convecting the sources of the input transistors of said differential stage, a pair of bias current generators, each coupled between the source of a respective input transistor and a common ground node, has said resistive line of degeneration composed of one or more transistors in series, the gate of which is coupled to a voltage at least equal to the common mode voltage of the differential stage, and which are sized to operate in the triode region.

    Abstract translation: 一种跨导体，包括由一对输入晶体管组成的差分级，与所述差分级的输入晶体管的源极对流的电阻线，一对偏置电流发生器，每个偏置电流发生器耦合在相应的输入晶体管的源极和 公共接地节点具有由串联的一个或多个晶体管组成的退化电阻线，其栅极耦合到至少等于差分级的共模电压的电压，并且其尺寸被设计成在三极管中工作 地区。

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