公开(公告)号：WO2003012983A1

公开(公告)日：2003-02-13

申请号：PCT/EP2002/007524

申请日：2002-07-05

Applicant: STMICROELECTRONICS S.R.L. ,  CONFALONIERI, Pierangelo ,  NICOLLINI, Germano ,  MARTIGNONE, Riccardo

Inventor： CONFALONIERI, Pierangelo ,  NICOLLINI, Germano ,  MARTIGNONE, Riccardo

IPC: H03F3/45

CPC classification number: H03F3/45937 ,  H03F1/303

Abstract: The circuit comprises a differential amplifier (10) with two inputs and two outputs and a common mode regulation circuit. Between a regulation terminal (INCM) of the amplifier and the outputs there are connected a first (C1p) and a second (1m) capacitor and first (C3) and second (C4) capacitive means that by means of controlled switches (SW9-SW12) can be alternatively and simultaneousy connected in parallel with, respectively, the first ((C1p) and the second (C1m) capacitor or between a first (VB) and a second (Vref1) reference voltage terminal. The capacitances C3 and C4 may be different in value such as to satisfy the following equality: Vcmn = Vref1 + '(Vrefp-Vrefm)/2!* (C4-C3)/(C3+C4), where Vcmn is the desired common mode output voltage, Vrefp and Vrefm are the differential output voltages and Vref1 is the voltage of the second reference terminal.are chosen in such a way as to satisfy the following equality : Vcmn = Vref1 + [(Vrefp-Vrefm)/2] * (C4-C3)/(C3+C4), where Vcmn is the desired common mode output voltage, Vrefp and Vrefm are the differential output voltages and Vref1 is the voltage of the second reference terminal.

Abstract translation: 该电路包括具有两个输入和两个输出的差分放大器（10）和一个共模调节电路。 在放大器的调节端子（INCM）和输出端之间连接有第一（C1p）和第二（1m）电容器以及通过受控开关（SW9-SW12）的第一（C3）和第二（C4）电容装置 ）可以分别与第一（（C1p）和第二（C1m）电容器或第一（VB）和第二（Vref1）参考电压端子并联连接，电容C3和C4可以是 不同的值，以满足以下等式：Vcmn = Vref1 +'（Vrefp-Vrefm）/ 2！*（C4-C3）/（C3 + C4），其中Vcmn是期望的共模输出电压，Vrefp和Vrefm 是差分输出电压，Vref1是第二参考端子的电压，以满足以下等式的方式选择：Vcmn = Vref1 + [（Vrefp-Vrefm）/ 2] *（C4-C3）/（ C3 + C4），其中Vcmn是所需的共模输出电压，Vrefp和Vrefm是差分输出电压，Vref1是秒的电压 参考端子。

公开(公告)号：WO2008023395A1

公开(公告)日：2008-02-28

申请号：PCT/IT2006/000628

申请日：2006-08-25

Applicant: STMICROELECTRONICS S.R.L. ,  ZAMPROGNO, Marco ,  NICOLLINI, Germano ,  MINUTI, Alberto

Inventor： ZAMPROGNO, Marco ,  NICOLLINI, Germano ,  MINUTI, Alberto

IPC: H03F3/00

CPC classification number: H03F1/3211 ,  H03F3/005 ,  H03F3/45475 ,  H03F3/45977 ,  H03F2203/45101 ,  H03F2203/45136 ,  H03F2203/45212 ,  H03F2203/45514

Abstract: An integrated buffer device (2) for a switched capacity circuit is described, comprising: - a buffer (7) having an output (OUT) for an output voltage dependent upon an input voltage (VIN) that can be supplied by a source (1) to the buffer device; - a capacitative switching component (C I ) that can be switched between a first and second condition in which it is connected, respectively, to the source and to the buffer to transfer the input voltage onto the output; said component being provided with a terminal (N2) having an associated stray capacity (C pi ). The device also comprises a charging and discharging device (SW CPIR , SW G ) configured to pre- charge the stray capacity at a reference voltage (REFM) before taking up the second condition and to pre-discharge the stray capacity before taking up the first condition.

Abstract translation: 描述了一种用于开关容量电路的集成缓冲器件（2），包括： - 缓冲器（7），其具有输出电压（OUT），该输出电压取决于可由源极（1）提供的输入电压（VIN） ）到缓冲装置; - 可以分别在其连接的第一和第二状态之间切换到电源和电容缓冲器以将输入电压传送到输出端的电容性开关部件（C SUB） 所述部件设置有具有相关联的杂散能力（C P1）的端子（N2）。 该装置还包括一个充电和放电装置（SW＆lt; CPIR＆gt;，＆lt;＆gt; G＆gt;），其被配置为在占用第二个参考电压之前对参考电压（REFM）预充电杂散容量 条件，并且在摄取第一个条件之前预先排出杂散容量。

公开(公告)号：WO2005117402A1

公开(公告)日：2005-12-08

申请号：PCT/IT2005/000281

申请日：2005-05-19

Applicant: STMICROELECTRONICS S.R.L. ,  NICOLLINI, Germano ,  CONFALONIERI, Pierangelo ,  MARTIGNONE, Riccardo

Inventor： NICOLLINI, Germano ,  CONFALONIERI, Pierangelo ,  MARTIGNONE, Riccardo

IPC: H04M1/74

CPC classification number: H04B1/707

Abstract: There is described a circuit for reconstructing an analog signal from a digital signal and wide-band transmission system, particularly for employment in cellular telephony systems, or more in general in mobile communication systems, that adopt the WCDMA standard. The circuit comprises: a digital to analog converter (DAC) suitable for receiving said digital signal and converting it into signal in analog.format; - a low pass-filter (LOW-PASS) connected at the output of said converter for receiving said signal in analog format and providing as output said reconstructed analog signal. Advantageously, the low pass filter (LOW-PASS) is an active filter continuous in time and current­ coupled to the output of the digital-analog converter (DAC) and the digital-analog converter (DAC) is a converter of the current-steering type functioning at sampling frequency greater than the Nyquist frequency of said analog signal to be reconstructed.

Abstract translation: 描述了一种用于从数字信号和宽带传输系统重建模拟信号的电路，特别是用于蜂窝电话系统中的用途，或更一般地在采用WCDMA标准的移动通信系统中。 该电路包括：适于接收所述数字信号并将其转换为模拟信号的数模转换器（DAC）; - 低通滤波器（LOW-PASS），连接在所述转换器的输出端，用于以模拟格式接收所述信号，并提供所述重构模拟信号的输出。 有利地，低通滤波器（LOW-PASS）是连续的数字模拟转换器（DAC）的输出端的时间和电流连续的有源滤波器，并且数模转换器（DAC）是电流转向器 在大于待重构的所述模拟信号的奈奎斯特频率的采样频率下工作。

公开(公告)号：EP3859975A1

公开(公告)日：2021-08-04

申请号：EP21151784.2

申请日：2021-01-15

Applicant: STMicroelectronics S.r.l.

Inventor： MODAFFARI, Roberto ,  PESENTI, Paolo ,  NICOLLINI, Germano

IPC: H03M3/02 ,  H03M3/04

Abstract: An excess loop delay (ELD) compensation network (120) for a sigma-delta modulator (10) comprises a derivative circuit (1202) configured to receive a weighed ( k 0C ) replica of the integrated signal ( y 1 ( t )) from the input integrator circuit (201) of the modulator and produce therefrom a derivative signal as well as a sign-reversal circuit (1204, 1206a, 1206b, φ C , φ C (neg)) configured to alternately reverse the sign of the derivative signal over subsequent time intervals of a duration half the sampling period (Ts) of the output quantizer circuit (A/D) of the modulator. A further integrator circuit (1208) is provided to integrate the derivative signal having alternately reversed sign along with an excess loop delay ( Z -τ ) compensation node (303) configured to inject into the signal propagation path (201, 302, 202, 303) towards the output quantizer circuit (A/D) an excess loop delay ( Z -τ ) compensation signal comprising the derivative signal after integration at the least one further integrator circuit (1208). Alternative embodiments may contemplate injecting the derivative signal into the signal propagation path towards the quantizer circuit (A/D) before integration of the derivative signal.

公开(公告)号：EP3361636B1

公开(公告)日：2020-07-29

申请号：EP17187803.6

申请日：2017-08-24

Applicant: STMicroelectronics S.r.l.

Inventor： RAMORINI, Stefano ,  NICOLLINI, Germano ,  CATTANI, Alberto ,  GASPARINI, Alessandro

IPC: H03K4/06 ,  H03F3/217

公开(公告)号：EP3185416B1

公开(公告)日：2020-01-01

申请号：EP16175666.3

申请日：2016-06-22

Applicant: STMicroelectronics S.r.l.

Inventor： NICOLLINI, Germano ,  GARBARINO, Marco

IPC: H03F3/70 ,  H03F3/45 ,  G01C19/5776 ,  H03K5/1536

公开(公告)号：EP2978241B1

公开(公告)日：2017-12-20

申请号：EP15177808.1

申请日：2015-07-22

Applicant: STMicroelectronics S.r.l.

Inventor： NICOLLINI, Germano ,  BARBIERI, Andrea ,  BARBIERI, Federica ,  DANIONI, Alberto ,  MARINO, Edoardo ,  PERNICI, Sergio

IPC: H04R3/00

CPC classification number: H04R19/04 ,  H04R3/00 ,  H04R2201/003

Abstract: Described herein is a MEMS acoustic transducer device (42) having: a capacitive microelectromechanical sensing structure (1) ; and a biasing circuit (20), including a voltage-boosting circuit (9) that supplies a boosted voltage (V CP ) on an output terminal (9a), and an insulating circuit element (10), defining a high impedance, set between the output terminal (9a) and a terminal of the sensing structure (1), which defines a first high-impedance node (N 1 ) associated to the insulating circuit element (10). The biasing circuit (20) has: a pre-charge stage (24) that generates at least one first pre-charge voltage (V pre1 ) on a first output (Out 1 ) thereof, as a function of, and distinct from, the boosted voltage (V CP ); and at least one first switch element (SW 1 ), set between the first output (Out 1 ) and the first high-impedance node (N 1 ). The first switch element (SW 1 ) is operable for selectively connecting the first high-impedance node (N 1 ) to the first output (Out 1 ), during a phase of start-up of the biasing circuit (20), for biasing the first high-impedance node to the first pre-charge voltage.

公开(公告)号：EP4339628A1

公开(公告)日：2024-03-20

申请号：EP23194464.6

申请日：2023-08-31

Applicant: STMicroelectronics S.r.l.

Inventor： NICOLLINI, Germano ,  VAIANA, Michele

IPC: G01R27/26

Abstract: A measurement system is described. The measurement system comprises a first capacitance (C 1 ), a second capacitance (C 2 ), a switching circuit (32a), a control circuit (36a) and a measurement circuit (34a). During a normal operating phase, the measurement system charges and discharges the first and second capacitances. For this purpose, the switching circuit (32a) and the control circuit (36a) periodically connect a first terminal of the first capacitance (C 1 ) to a first voltage (V 1 ) and a reference voltage (V ref ), and similarly a first terminal of the second capacitance (C 2 ) to a second voltage (V 2 ) and the reference voltage (V ref ). Conversely, the second terminal of the first capacitance (C 1 ) and the second terminal of the second capacitance (C 2 ) are connected to the input terminals of a differential operational amplifier (3440) of the differential integrator, whereby the charge difference between the capacitances (Ci, C 2 ) is transferred to the differential integrator. In this respect, a comparator with hysteresis (3446) triggers when the output signal of the differential integrator exceeds the hysteresis threshold of the comparator with hysteresis (3446).
In particular, two decoupling capacitances (C DEC1 , C DEC2 ) are connected between the input of the comparator with hysteresis (3446) and the output of the differential integrator, and the measurement systems uses two reset phases in order to store various disturbances to these decoupling capacitances (C DEC1 , C DEC2 ), thereby improving the precision of the measurement during the normal operating phase.

公开(公告)号：EP2978241A1

公开(公告)日：2016-01-27

申请号：EP15177808.1

申请日：2015-07-22

Applicant: STMicroelectronics S.r.l.

Inventor： NICOLLINI, Germano ,  BARBIERI, Andrea ,  BARBIERI, Federica ,  DANIONI, Alberto ,  MARINO, Edoardo ,  PERNICI, Sergio

IPC: H04R3/00

CPC classification number: H04R19/04 ,  H04R3/00 ,  H04R2201/003

Abstract: Described herein is a MEMS acoustic transducer device (42) having: a capacitive microelectromechanical sensing structure (1) ; and a biasing circuit (20), including a voltage-boosting circuit (9) that supplies a boosted voltage (V CP ) on an output terminal (9a), and an insulating circuit element (10), defining a high impedance, set between the output terminal (9a) and a terminal of the sensing structure (1), which defines a first high-impedance node (N 1 ) associated to the insulating circuit element (10). The biasing circuit (20) has: a pre-charge stage (24) that generates at least one first pre-charge voltage (V pre1 ) on a first output (Out 1 ) thereof, as a function of, and distinct from, the boosted voltage (V CP ); and at least one first switch element (SW 1 ), set between the first output (Out 1 ) and the first high-impedance node (N 1 ). The first switch element (SW 1 ) is operable for selectively connecting the first high-impedance node (N 1 ) to the first output (Out 1 ), during a phase of start-up of the biasing circuit (20), for biasing the first high-impedance node to the first pre-charge voltage.

Abstract translation: 这里描述的是一种MEMS声学换能器装置（42），其具有：电容性微机电感测结构（1）; 以及偏置电路（20），其包括在输出端子（9a）上提供升压电压（V CP）的升压电路（9）和限定高阻抗的绝缘电路元件（10），所述绝缘电路元件 输出端子（9a）和感测结构（1）的端子，其限定与绝缘电路元件（10）相关联的第一高阻抗节点（N 1）。 偏置电路（20）具有：预充电阶段（24），其在其第一输出（Out 1）上产生至少一个第一预充电电压（V pre1），作为和/ 升压电压（V CP）; 以及设置在第一输出（Out 1）和第一高阻抗节点（N1）之间的至少一个第一开关元件（SW 1）。 第一开关元件（SW 1）可操作用于在偏置电路（20）的启动阶段期间选​​择性地将第一高阻抗节点（N1）连接到第一输出（输出1），以便偏置 第一个高阻抗节点到第一个预充电电压。

公开(公告)号：EP2055000A2

公开(公告)日：2009-05-06

申请号：EP06796269.6

申请日：2006-08-25

Applicant: STMicroelectronics S.r.l.

Inventor： ZAMPROGNO, Marco ,  NICOLLINI, Germano ,  MINUTI, Alberto

IPC: H03F3/00

CPC classification number: H03F1/3211 ,  H03F3/005 ,  H03F3/45475 ,  H03F3/45977 ,  H03F2203/45101 ,  H03F2203/45136 ,  H03F2203/45212 ,  H03F2203/45514

Abstract: An integrated buffer device (2) for a switched capacity circuit is described, comprising: - a buffer (7) having an output (OUT) for an output voltage dependent upon an input voltage (VIN) that can be supplied by a source (1) to the buffer device; - a capacitative switching component (CI) that can be switched between a first and second condition in which it is connected, respectively, to the source and to the buffer to transfer the input voltage onto the output; said component being provided with a terminal (N2) having an associated stray capacity (Cpi). The device also comprises a charging and discharging device (SWCPIR, SWG) configured to pre- charge the stray capacity at a reference voltage (REFM) before taking up the second condition and to pre-discharge the stray capacity before taking up the first condition.